-/**************************************************************************
- *
+/*
* Copyright 2006 VMware, Inc.
* All Rights Reserved.
*
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
+ * distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
+ */
/** @file intel_mipmap_tree.h
*
struct intel_texture_image;
/**
+ * This bit extends the set of GL_MAP_*_BIT enums.
+ *
* When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
* depthstencil-split-to-separate-stencil miptree, we'll normally make a
- * tmeporary and recreate the kind of data requested by Mesa core, since we're
+ * temporary and recreate the kind of data requested by Mesa core, since we're
* satisfying some glGetTexImage() request or something.
*
* However, occasionally you want to actually map the miptree's current data
#define BRW_MAP_DIRECT_BIT 0x80000000
struct intel_miptree_map {
- /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
+ /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
GLbitfield mode;
/** Region of interest for the map. */
int x, y, w, h;
/** Possibly malloced temporary buffer for the mapping. */
void *buffer;
/** Possible pointer to a temporary linear miptree for the mapping. */
- struct intel_mipmap_tree *mt;
+ struct intel_mipmap_tree *linear_mt;
/** Pointer to the start of (map_x, map_y) returned by the mapping. */
void *ptr;
/** Stride of the mapping. */
* \code
* x = mt->level[l].slice[s].x_offset
* y = mt->level[l].slice[s].y_offset
+ *
+ * On some hardware generations, we program these offsets into
+ * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
*/
GLuint x_offset;
GLuint y_offset;
* accommodated by scaling up the width and the height of the surface so
* that all the samples corresponding to a pixel are located at nearby
* memory locations.
+ *
+ * @see PRM section "Interleaved Multisampled Surfaces"
*/
INTEL_MSAA_LAYOUT_IMS,
/**
* Uncompressed Multisample Surface. The surface is stored as a 2D array,
* with array slice n containing all pixel data for sample n.
+ *
+ * @see PRM section "Uncompressed Multisampled Surfaces"
*/
INTEL_MSAA_LAYOUT_UMS,
* the common case (where all samples constituting a pixel have the same
* color value) to be stored efficiently by just using a single array
* slice.
+ *
+ * @see PRM section "Compressed Multisampled Surfaces"
*/
INTEL_MSAA_LAYOUT_CMS,
};
*/
struct intel_miptree_aux_buffer
{
- /** Buffer object containing the pixel data. */
+ /**
+ * Buffer object containing the pixel data.
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
+ */
drm_intel_bo *bo;
- uint32_t pitch; /**< pitch in bytes. */
+ /**
+ * Pitch in bytes.
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
+ */
+ uint32_t pitch;
- uint32_t qpitch; /**< The distance in rows between array slices. */
+ /**
+ * The distance in rows between array slices.
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
+ */
+ uint32_t qpitch;
- struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
+ /**
+ * Hiz miptree. Used only by Gen6.
+ */
+ struct intel_mipmap_tree *mt;
};
/* Tile resource modes */
struct intel_mipmap_tree
{
- /** Buffer object containing the pixel data. */
+ /**
+ * Buffer object containing the surface.
+ *
+ * @see intel_mipmap_tree::offset
+ * @see RENDER_SURFACE_STATE.SurfaceBaseAddress
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
+ */
drm_intel_bo *bo;
- uint32_t pitch; /**< pitch in bytes. */
+ /**
+ * Pitch in bytes.
+ *
+ * @see RENDER_SURFACE_STATE.SurfacePitch
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
+ * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
+ * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
+ */
+ uint32_t pitch;
- uint32_t tiling; /**< One of the I915_TILING_* flags */
+ /**
+ * One of the I915_TILING_* flags.
+ *
+ * @see RENDER_SURFACE_STATE.TileMode
+ * @see 3DSTATE_DEPTH_BUFFER.TileMode
+ */
+ uint32_t tiling;
+
+ /**
+ * @see RENDER_SURFACE_STATE.TiledResourceMode
+ * @see 3DSTATE_DEPTH_BUFFER.TiledResourceMode
+ */
enum intel_miptree_tr_mode tr_mode;
- /* Effectively the key:
+ /**
+ * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
+ *
+ * @see RENDER_SURFACE_STATE.SurfaceType
+ * @see RENDER_SURFACE_STATE.SurfaceArray
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceType
*/
GLenum target;
*
* For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
* formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
+ *
+ * @see RENDER_SURFACE_STATE.SurfaceFormat
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceFormat
*/
mesa_format format;
- /** This variable stores the value of ETC compressed texture format */
+ /**
+ * This variable stores the value of ETC compressed texture format
+ *
+ * @see RENDER_SURFACE_STATE.SurfaceFormat
+ */
mesa_format etc_format;
/**
- * The X offset of each image in the miptree must be aligned to this.
- * See the comments in brw_tex_layout.c.
+ * @name Surface Alignment
+ * @{
+ *
+ * This defines the alignment of the upperleft pixel of each "slice" in the
+ * surface. The alignment is in pixel coordinates relative to the surface's
+ * most upperleft pixel, which is the pixel at (x=0, y=0, layer=0,
+ * level=0).
+ *
+ * The hardware docs do not use the term "slice". We use "slice" to mean
+ * the pixels at a given miplevel and layer. For 2D surfaces, the layer is
+ * the array slice; for 3D surfaces, the layer is the z offset.
+ *
+ * In the surface layout equations found in the hardware docs, the
+ * horizontal and vertical surface alignments often appear as variables 'i'
+ * and 'j'.
*/
- unsigned int align_w;
- unsigned int align_h; /**< \see align_w */
+
+ /** @see RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
+ uint32_t halign;
+
+ /** @see RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
+ uint32_t valign;
+ /** @} */
GLuint first_level;
GLuint last_level;
*/
GLuint physical_width0, physical_height0, physical_depth0;
- GLuint cpp; /**< bytes per pixel */
+ /** Bytes per pixel (or bytes per block if compressed) */
+ GLuint cpp;
+
+ /**
+ * @see RENDER_SURFACE_STATE.NumberOfMultisamples
+ * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
+ */
GLuint num_samples;
+
bool compressed;
/**
- * Level zero image dimensions. These dimensions correspond to the
+ * @name Level zero image dimensions
+ * @{
+ *
+ * These dimensions correspond to the
* logical width, height, and depth of the texture as seen by client code.
* Accordingly, they do not account for the extra width, height, and/or
* depth that must be allocated in order to accommodate multisample
* formats, nor do they account for the extra factor of 6 in depth that
* must be allocated in order to accommodate cubemap textures.
*/
- uint32_t logical_width0, logical_height0, logical_depth0;
+
+ /**
+ * @see RENDER_SURFACE_STATE.Width
+ * @see 3DSTATE_DEPTH_BUFFER.Width
+ */
+ uint32_t logical_width0;
+
+ /**
+ * @see RENDER_SURFACE_STATE.Height
+ * @see 3DSTATE_DEPTH_BUFFER.Height
+ */
+ uint32_t logical_height0;
+
+ /**
+ * @see RENDER_SURFACE_STATE.Depth
+ * @see 3DSTATE_DEPTH_BUFFER.Depth
+ */
+ uint32_t logical_depth0;
+ /** @} */
/**
* Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
* surfaces it is the number of blocks. For 1D array surfaces that have the
* mipmap tree stored horizontally it is the number of pixels between each
* slice.
+ *
+ * @see RENDER_SURFACE_STATE.SurfaceQPitch
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceQPitch
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
+ * @see 3DSTATE_STENCIL_BUFFER.SurfaceQPitch
*/
uint32_t qpitch;
/**
* MSAA layout used by this buffer.
+ *
+ * @see RENDER_SURFACE_STATE.MultisampledSurfaceStorageFormat
*/
enum intel_msaa_layout msaa_layout;
GLuint total_width;
GLuint total_height;
- /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
- * this depth mipmap tree, if any.
+ /**
+ * The depth value used during the most recent fast depth clear performed
+ * on the surface. This field is invalid only if surface has never
+ * underwent a fast depth clear.
+ *
+ * @see 3DSTATE_CLEAR_PARAMS.DepthClearValue
*/
uint32_t depth_clear_value;
- /* Includes image offset tables:
- */
+ /* Includes image offset tables: */
struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
- /* Offset into bo where miptree starts:
+ /**
+ * Offset into bo where the surface starts.
+ *
+ * @see intel_mipmap_tree::bo
+ *
+ * @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+ * @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
+ * @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
*/
uint32_t offset;
/**
* \brief HiZ aux buffer
*
- * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
- * buffer, use intel_miptree_alloc_hiz().
+ * To allocate the hiz buffer, use intel_miptree_alloc_hiz().
*
* To determine if hiz is enabled, do not check this pointer. Instead, use
* intel_miptree_slice_has_hiz().
* require separate stencil. It always has the true copy of the stencil
* bits, regardless of mt->format.
*
+ * \see 3DSTATE_STENCIL_BUFFER
* \see intel_miptree_map_depthstencil()
* \see intel_miptree_unmap_depthstencil()
*/
* The SURFACE_STATE bits associated with the last fast color clear to this
* color mipmap tree, if any.
*
- * This value will only ever contain ones in bits 28-31, so it is safe to
- * OR into dword 7 of SURFACE_STATE.
+ * Prior to GEN9 there is a single bit for RGBA clear values which gives you
+ * the option of 2^4 clear colors. Each bit determines if the color channel
+ * is fully saturated or unsaturated (Cherryview does add a 32b value per
+ * channel, but it is globally applied instead of being part of the render
+ * surface state). Starting with GEN9, the surface state accepts a 32b value
+ * for each color channel.
+ *
+ * @see RENDER_SURFACE_STATE.RedClearColor
+ * @see RENDER_SURFACE_STATE.GreenClearColor
+ * @see RENDER_SURFACE_STATE.BlueClearColor
+ * @see RENDER_SURFACE_STATE.AlphaClearColor
*/
- uint32_t fast_clear_color_value;
+ union {
+ uint32_t fast_clear_color_value;
+ union gl_color_union gen9_fast_clear_color;
+ };
/**
* Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
GLuint refcount;
};
-enum intel_miptree_tiling_mode {
- INTEL_MIPTREE_TILING_ANY,
- INTEL_MIPTREE_TILING_Y,
- INTEL_MIPTREE_TILING_NONE,
-};
-
void
-intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
+intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
unsigned *width_px, unsigned *height);
+
bool
-intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling);
+intel_miptree_is_lossless_compressed(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt);
+
bool
-intel_miptree_is_fast_clear_capable(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
+intel_tiling_supports_non_msrt_mcs(const struct brw_context *brw,
+ unsigned tiling);
+
+bool
+intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt);
+
+bool
+intel_miptree_supports_lossless_compressed(struct brw_context *brw,
+ const struct intel_mipmap_tree *mt);
+
bool
intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt);
MIPTREE_LAYOUT_FOR_BO = 1 << 2,
MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
+
+ MIPTREE_LAYOUT_TILING_Y = 1 << 5,
+ MIPTREE_LAYOUT_TILING_NONE = 1 << 6,
+ MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y |
+ MIPTREE_LAYOUT_TILING_NONE,
};
struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
GLuint height0,
GLuint depth0,
GLuint num_samples,
- enum intel_miptree_tiling_mode,
uint32_t flags);
struct intel_mipmap_tree *
uint32_t level,
uint32_t layer)
{
+ (void) mt;
+ (void) level;
+ (void) layer;
+
assert(level >= mt->first_level);
assert(level <= mt->last_level);
assert(layer < mt->level[level].depth);
GLuint *x, GLuint *y);
void
-intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
- int *width, int *height, int *depth);
+intel_get_image_dims(struct gl_texture_image *image,
+ int *width, int *height, int *depth);
+
+void
+intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+ bool map_stencil_as_y_tiled,
+ uint32_t *mask_x, uint32_t *mask_y);
void
-intel_miptree_get_tile_masks(const struct intel_mipmap_tree *mt,
- uint32_t *mask_x, uint32_t *mask_y,
- bool map_stencil_as_y_tiled);
+intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
+ uint32_t *tile_w, uint32_t *tile_h);
uint32_t
intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
}
+/**
+ * Flag values telling color resolve pass which special types of buffers
+ * can be ignored.
+ *
+ * INTEL_MIPTREE_IGNORE_CCS_E: Lossless compressed (single-sample
+ * compression scheme since gen9)
+ */
+#define INTEL_MIPTREE_IGNORE_CCS_E (1 << 0)
+
void
intel_miptree_resolve_color(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
+ struct intel_mipmap_tree *mt,
+ int flags);
void
intel_miptree_make_shareable(struct brw_context *brw,
void
brw_miptree_layout(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- enum intel_miptree_tiling_mode requested,
uint32_t layout_flags);
-void *intel_miptree_map_raw(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
-void intel_miptree_unmap_raw(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
void
intel_miptree_map(struct brw_context *brw,
struct intel_mipmap_tree *mt,
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