ALL_SLICES_AT_EACH_LOD,
};
+/**
+ * Miptree aux buffer. These buffers are associated with a miptree, but the
+ * format is managed by the hardware.
+ *
+ * For Gen7+, we always give the hardware the start of the buffer, and let it
+ * handle all accesses to the buffer. Therefore we don't need the full miptree
+ * layout structure for this buffer.
+ *
+ * For Gen6, we need a hiz miptree structure for this buffer so we can program
+ * offsets to slices & miplevels.
+ */
+struct intel_miptree_aux_buffer
+{
+ /** Buffer object containing the pixel data. */
+ drm_intel_bo *bo;
+
+ uint32_t pitch; /**< pitch in bytes. */
+
+ uint32_t qpitch; /**< The distance in rows between array slices. */
+
+ struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
+};
+
+/* Tile resource modes */
+enum intel_miptree_tr_mode {
+ INTEL_MIPTREE_TRMODE_NONE,
+ INTEL_MIPTREE_TRMODE_YF,
+ INTEL_MIPTREE_TRMODE_YS
+};
+
struct intel_mipmap_tree
{
/** Buffer object containing the pixel data. */
uint32_t pitch; /**< pitch in bytes. */
uint32_t tiling; /**< One of the I915_TILING_* flags */
+ enum intel_miptree_tr_mode tr_mode;
/* Effectively the key:
*/
enum miptree_array_layout array_layout;
/**
- * The distance in rows between array slices in an uncompressed surface.
+ * The distance in between array slices.
*
- * For compressed surfaces, slices are stored closer together physically;
- * the real distance is (qpitch / block height).
+ * The value is the one that is sent in the surface state. The actual
+ * meaning depends on certain criteria. Usually it is simply the number of
+ * uncompressed rows between each slice. However on Gen9+ for compressed
+ * surfaces it is the number of blocks. For 1D array surfaces that have the
+ * mipmap tree stored horizontally it is the number of pixels between each
+ * slice.
*/
uint32_t qpitch;
uint32_t offset;
/**
- * \brief HiZ miptree
+ * \brief HiZ aux buffer
*
* The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
- * miptree, use intel_miptree_alloc_hiz().
+ * buffer, use intel_miptree_alloc_hiz().
*
* To determine if hiz is enabled, do not check this pointer. Instead, use
* intel_miptree_slice_has_hiz().
*/
- struct intel_mipmap_tree *hiz_mt;
+ struct intel_miptree_aux_buffer *hiz_buf;
/**
* \brief Map of miptree slices to needed resolves.
*/
uint32_t fast_clear_color_value;
+ /**
+ * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
+ * buffer. This is useful for sharing the miptree bo with an external client
+ * that doesn't understand auxiliary buffers.
+ */
+ bool disable_aux_buffers;
+
/* These are also refcounted:
*/
GLuint refcount;
};
-enum intel_miptree_tiling_mode {
- INTEL_MIPTREE_TILING_ANY,
- INTEL_MIPTREE_TILING_Y,
- INTEL_MIPTREE_TILING_NONE,
-};
-
-bool
-intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
- struct intel_mipmap_tree *mt);
-
void
intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned *width_px, unsigned *height);
-
+bool
+intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling);
+bool
+intel_miptree_is_fast_clear_capable(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
bool
intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt);
+enum {
+ MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
+ MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD = 1 << 1,
+ MIPTREE_LAYOUT_FOR_BO = 1 << 2,
+ MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
+ MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
+
+ MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5,
+ MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6,
+ MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7,
+};
+
+#define MIPTREE_LAYOUT_ALLOC_ANY_TILED (MIPTREE_LAYOUT_ALLOC_YTILED | \
+ MIPTREE_LAYOUT_ALLOC_XTILED)
+
struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
GLenum target,
mesa_format format,
GLuint width0,
GLuint height0,
GLuint depth0,
- bool expect_accelerated_upload,
GLuint num_samples,
- enum intel_miptree_tiling_mode,
- bool force_all_slices_at_each_lod);
-
-struct intel_mipmap_tree *
-intel_miptree_create_layout(struct brw_context *brw,
- GLenum target,
- mesa_format format,
- GLuint first_level,
- GLuint last_level,
- GLuint width0,
- GLuint height0,
- GLuint depth0,
- bool for_bo,
- GLuint num_samples,
- bool force_all_slices_at_each_lod);
+ uint32_t flags);
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t offset,
uint32_t width,
uint32_t height,
- int pitch);
+ uint32_t depth,
+ int pitch,
+ uint32_t layout_flags);
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_texture_image *intelImage,
struct intel_mipmap_tree *dst_mt, bool invalidate);
-bool
-intel_miptree_alloc_mcs(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- GLuint num_samples);
-
/**
* \name Miptree HiZ functions
* \{
* functions on a miptree without HiZ. In that case, each function is a no-op.
*/
+bool
+intel_miptree_wants_hiz_buffer(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
+
/**
* \brief Allocate the miptree's embedded HiZ miptree.
* \see intel_mipmap_tree:hiz_mt
* \return false if allocation failed
*/
-
bool
intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt);
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);
-void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
+/**
+ * Horizontal distance from one slice to the next in the two-dimensional
+ * miptree layout.
+ */
+unsigned
+brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ unsigned level);
+
+/**
+ * Vertical distance from one slice to the next in the two-dimensional miptree
+ * layout.
+ */
+unsigned
+brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ unsigned level);
+
+void
+brw_miptree_layout(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t layout_flags);
void *intel_miptree_map_raw(struct brw_context *brw,
struct intel_mipmap_tree *mt);
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