i965: Enable L3 caching of buffer surfaces.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_mipmap_tree.h

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index bb040845d51dd5478c911a069d8586bd279ad114..ee9cf1ea4a9a892fdae17a97e1677b64b1400946 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -255,6 +255,58 @@ enum intel_fast_clear_state
    INTEL_FAST_CLEAR_STATE_CLEAR,
 };
 
+enum miptree_array_layout {
+   /* Each array slice contains all miplevels packed together.
+    *
+    * Gen hardware usually wants multilevel miptrees configured this way.
+    *
+    * A 2D Array texture with 2 slices and multiple LODs using
+    * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
+    *
+    *   +----------+
+    *   |          |
+    *   |          |
+    *   +----------+
+    *   +---+ +-+
+    *   |   | +-+
+    *   +---+ *
+    *   +----------+
+    *   |          |
+    *   |          |
+    *   +----------+
+    *   +---+ +-+
+    *   |   | +-+
+    *   +---+ *
+    */
+   ALL_LOD_IN_EACH_SLICE,
+
+   /* Each LOD contains all slices of that LOD packed together.
+    *
+    * In some situations, Gen7+ hardware can use the array_spacing_lod0
+    * feature to save space when the surface only contains LOD 0.
+    *
+    * Gen6 uses this for separate stencil and hiz since gen6 does not support
+    * multiple LODs for separate stencil and hiz.
+    *
+    * A 2D Array texture with 2 slices and multiple LODs using
+    * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
+    *
+    *   +----------+
+    *   |          |
+    *   |          |
+    *   +----------+
+    *   |          |
+    *   |          |
+    *   +----------+
+    *   +---+ +-+
+    *   |   | +-+
+    *   +---+ +-+
+    *   |   | :
+    *   +---+
+    */
+   ALL_SLICES_AT_EACH_LOD,
+};
+
 struct intel_mipmap_tree
 {
    /** Buffer object containing the pixel data. */
@@ -322,13 +374,10 @@ struct intel_mipmap_tree
    uint32_t logical_width0, logical_height0, logical_depth0;
 
    /**
-    * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
-    * if the surface only contains LOD 0, and hence no space is for LOD's
-    * other than 0 in between array slices.
-    *
-    * Corresponds to the surface_array_spacing bit in gen7_surface_state.
+    * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
+    * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
     */
-   bool array_spacing_lod0;
+   enum miptree_array_layout array_layout;
 
    /**
     * The distance in rows between array slices in an uncompressed surface.
@@ -454,7 +503,8 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
                                                GLuint depth0,
                                               bool expect_accelerated_upload,
                                                GLuint num_samples,
-                                               enum intel_miptree_tiling_mode);
+                                               enum intel_miptree_tiling_mode,
+                                               bool force_all_slices_at_each_lod);
 
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct brw_context *brw,
@@ -466,7 +516,8 @@ intel_miptree_create_layout(struct brw_context *brw,
                             GLuint height0,
                             GLuint depth0,
                             bool for_bo,
-                            GLuint num_samples);
+                            GLuint num_samples,
+                            bool force_all_slices_at_each_lod);
 
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct brw_context *brw,
@@ -475,6 +526,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
                             uint32_t offset,
                             uint32_t width,
                             uint32_t height,
+                            uint32_t depth,
                             int pitch);
 
 void
@@ -682,7 +734,7 @@ intel_miptree_map(struct brw_context *brw,
                  unsigned int h,
                  GLbitfield mode,
                  void **out_ptr,
-                 int *out_stride);
+                 ptrdiff_t *out_stride);
 
 void
 intel_miptree_unmap(struct brw_context *brw,