*
**************************************************************************/
+/** @file intel_mipmap_tree.h
+ *
+ * This file defines the structure that wraps a BO and describes how the
+ * mipmap levels and slices of a texture are laid out.
+ *
+ * The hardware has a fixed layout of a texture depending on parameters such
+ * as the target/type (2D, 3D, CUBE), width, height, pitch, and number of
+ * mipmap levels. The individual level/layer slices are each 2D rectangles of
+ * pixels at some x/y offset from the start of the drm_intel_bo.
+ *
+ * Original OpenGL allowed texture miplevels to be specified in arbitrary
+ * order, and a texture may change size over time. Thus, each
+ * intel_texture_image has a reference to a miptree that contains the pixel
+ * data sized appropriately for it, which will later be referenced by/copied
+ * to the intel_texture_object at draw time (intel_finalize_mipmap_tree()) so
+ * that there's a single miptree for the complete texture.
+ */
+
#ifndef INTEL_MIPMAP_TREE_H
#define INTEL_MIPMAP_TREE_H
#include <assert.h>
-#include "intel_regions.h"
+#include "main/mtypes.h"
+#include "intel_bufmgr.h"
#include "intel_resolve_map.h"
#include <GL/internal/dri_interface.h>
extern "C" {
#endif
+struct brw_context;
struct intel_renderbuffer;
-/* A layer on top of the intel_regions code which adds:
- *
- * - Code to size and layout a region to hold a set of mipmaps.
- * - Query to determine if a new image fits in an existing tree.
- * - More refcounting
- * - maybe able to remove refcounting from intel_region?
- * - ?
- *
- * The fixed mipmap layout of intel hardware where one offset
- * specifies the position of all images in a mipmap hierachy
- * complicates the implementation of GL texture image commands,
- * compared to hardware where each image is specified with an
- * independent offset.
- *
- * In an ideal world, each texture object would be associated with a
- * single bufmgr buffer or 2d intel_region, and all the images within
- * the texture object would slot into the tree as they arrive. The
- * reality can be a little messier, as images can arrive from the user
- * with sizes that don't fit in the existing tree, or in an order
- * where the tree layout cannot be guessed immediately.
- *
- * This structure encodes an idealized mipmap tree. The GL image
- * commands build these where possible, otherwise store the images in
- * temporary system buffers.
- */
-
struct intel_resolve_map;
struct intel_texture_image;
};
/**
- * Describes the location of each texture image within a texture region.
+ * Describes the location of each texture image within a miptree.
*/
struct intel_mipmap_level
{
*/
GLuint depth;
+ /**
+ * \brief Is HiZ enabled for this level?
+ *
+ * If \c mt->level[l].has_hiz is set, then (1) \c mt->hiz_mt has been
+ * allocated and (2) the HiZ memory for the slices in this level reside at
+ * \c mt->hiz_mt->level[l].
+ */
+ bool has_hiz;
+
/**
* \brief List of 2D images in this mipmap level.
*
* intel_miptree_map/unmap on this slice.
*/
struct intel_miptree_map *map;
-
- /**
- * \brief Is HiZ enabled for this slice?
- *
- * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
- * has been allocated and (2) the HiZ memory corresponding to this slice
- * resides at \c mt->hiz_mt->level[l].slice[s].
- */
- bool has_hiz;
} *slice;
};
INTEL_FAST_CLEAR_STATE_CLEAR,
};
+enum miptree_array_layout {
+ /* Each array slice contains all miplevels packed together.
+ *
+ * Gen hardware usually wants multilevel miptrees configured this way.
+ *
+ * A 2D Array texture with 2 slices and multiple LODs using
+ * ALL_LOD_IN_EACH_SLICE would look somewhat like this:
+ *
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * +---+ +-+
+ * | | +-+
+ * +---+ *
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * +---+ +-+
+ * | | +-+
+ * +---+ *
+ */
+ ALL_LOD_IN_EACH_SLICE,
+
+ /* Each LOD contains all slices of that LOD packed together.
+ *
+ * In some situations, Gen7+ hardware can use the array_spacing_lod0
+ * feature to save space when the surface only contains LOD 0.
+ *
+ * Gen6 uses this for separate stencil and hiz since gen6 does not support
+ * multiple LODs for separate stencil and hiz.
+ *
+ * A 2D Array texture with 2 slices and multiple LODs using
+ * ALL_SLICES_AT_EACH_LOD would look somewhat like this:
+ *
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * | |
+ * | |
+ * +----------+
+ * +---+ +-+
+ * | | +-+
+ * +---+ +-+
+ * | | :
+ * +---+
+ */
+ ALL_SLICES_AT_EACH_LOD,
+};
+
struct intel_mipmap_tree
{
+ /** Buffer object containing the pixel data. */
+ drm_intel_bo *bo;
+
+ uint32_t pitch; /**< pitch in bytes. */
+
+ uint32_t tiling; /**< One of the I915_TILING_* flags */
+
/* Effectively the key:
*/
GLenum target;
* MESA_FORMAT_Z24_UNORM_X8_UINT.
*
* For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
- * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
+ * formats if the hardware lacks support for ETC1/ETC2. See @ref etc_format.
*/
mesa_format format;
*/
GLuint physical_width0, physical_height0, physical_depth0;
- GLuint cpp;
+ GLuint cpp; /**< bytes per pixel */
GLuint num_samples;
bool compressed;
/**
* Level zero image dimensions. These dimensions correspond to the
- * logical width, height, and depth of the region as seen by client code.
+ * logical width, height, and depth of the texture as seen by client code.
* Accordingly, they do not account for the extra width, height, and/or
* depth that must be allocated in order to accommodate multisample
* formats, nor do they account for the extra factor of 6 in depth that
uint32_t logical_width0, logical_height0, logical_depth0;
/**
- * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
- * if the surface only contains LOD 0, and hence no space is for LOD's
- * other than 0 in between array slices.
- *
- * Corresponds to the surface_array_spacing bit in gen7_surface_state.
+ * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
+ * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
*/
- bool array_spacing_lod0;
+ enum miptree_array_layout array_layout;
/**
* The distance in rows between array slices in an uncompressed surface.
*/
struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
- /* The data is held here:
- */
- struct intel_region *region;
-
- /* Offset into region bo where miptree starts:
+ /* Offset into bo where miptree starts:
*/
uint32_t offset;
* \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
* mt->hiz_mt->hiz_map, is unused.
*/
- struct intel_resolve_map hiz_map;
+ struct exec_list hiz_map; /* List of intel_resolve_map. */
/**
* \brief Stencil miptree for depthstencil textures.
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
- enum intel_miptree_tiling_mode);
+ enum intel_miptree_tiling_mode,
+ bool force_all_slices_at_each_lod);
struct intel_mipmap_tree *
intel_miptree_create_layout(struct brw_context *brw,
GLuint height0,
GLuint depth0,
bool for_bo,
- GLuint num_samples);
+ GLuint num_samples,
+ bool force_all_slices_at_each_lod);
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t offset,
uint32_t width,
uint32_t height,
- int pitch,
- uint32_t tiling);
+ uint32_t depth,
+ int pitch);
void
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_renderbuffer *irb,
- struct intel_region *region);
+ drm_intel_bo *bo,
+ uint32_t width, uint32_t height,
+ uint32_t pitch);
/**
* Create a miptree appropriate as the storage for a non-texture renderbuffer.
GLuint level, GLuint slice,
uint32_t *tile_x,
uint32_t *tile_y);
+uint32_t
+intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
+ uint32_t x, uint32_t y,
+ bool map_stencil_as_y_tiled);
void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
GLuint level,
struct intel_mipmap_tree *mt);
bool
-intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
- uint32_t level,
- uint32_t layer);
+intel_miptree_level_has_hiz(struct intel_mipmap_tree *mt, uint32_t level);
void
intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
unsigned int h,
GLbitfield mode,
void **out_ptr,
- int *out_stride);
+ ptrdiff_t *out_stride);
void
intel_miptree_unmap(struct brw_context *brw,
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