i965: Add #defines for the MI_LOAD_REGISTER_MEM command.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_reg.h

diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
index 470f61c41c1a8fd76d2ad955d2557d5672c36cf8..d73203892cf4bf4e0d4ef34d735413c3e76f46ea 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@ -44,6 +44,10 @@
 #define MI_STORE_REGISTER_MEM          (CMD_MI | (0x24 << 23))
 # define MI_STORE_REGISTER_MEM_USE_GGTT                (1 << 22)
 
+/* Load a value from memory into a register.  Only available on Gen7+. */
+#define GEN7_MI_LOAD_REGISTER_MEM      (CMD_MI | (0x29 << 23))
+# define MI_LOAD_REGISTER_MEM_USE_GGTT         (1 << 22)
+
 /** @{
  *
  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
@@ -109,11 +113,8 @@
 #define PS_INVOCATION_COUNT             0x2348
 #define PS_DEPTH_COUNT                  0x2350
 
-#define SO_NUM_PRIM_STORAGE_NEEDED     0x2280
-#define SO_PRIM_STORAGE_NEEDED0_IVB    0x5240
-#define SO_PRIM_STORAGE_NEEDED1_IVB    0x5248
-#define SO_PRIM_STORAGE_NEEDED2_IVB    0x5250
-#define SO_PRIM_STORAGE_NEEDED3_IVB    0x5258
+#define GEN6_SO_PRIM_STORAGE_NEEDED     0x2280
+#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
 
 #define GEN6_SO_NUM_PRIMS_WRITTEN       0x2288
 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)    (0x5200 + (n) * 8)