#include "main/version.h"
#include "swrast/s_renderbuffer.h"
#include "util/ralloc.h"
-#include "brw_shader.h"
+#include "brw_defines.h"
#include "compiler/nir/nir.h"
#include "utils.h"
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
DRI_CONF_DISABLE_THROTTLING("false")
DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
+ DRI_CONF_FORCE_GLSL_VERSION(0)
DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
+ DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
DRI_CONF_DESC(en, "Perform code generation at shader link time.")
return tp.tv_sec + tp.tv_nsec / 1000000000.0;
}
-void
-aub_dump_bmp(struct gl_context *ctx)
-{
- struct gl_framebuffer *fb = ctx->DrawBuffer;
-
- for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
- struct intel_renderbuffer *irb =
- intel_renderbuffer(fb->_ColorDrawBuffers[i]);
-
- if (irb && irb->mt) {
- enum aub_dump_bmp_format format;
-
- switch (irb->Base.Base.Format) {
- case MESA_FORMAT_B8G8R8A8_UNORM:
- case MESA_FORMAT_B8G8R8X8_UNORM:
- format = AUB_DUMP_BMP_FORMAT_ARGB_8888;
- break;
- default:
- continue;
- }
-
- drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo,
- irb->draw_x,
- irb->draw_y,
- irb->Base.Base.Width,
- irb->Base.Base.Height,
- format,
- irb->mt->pitch,
- 0);
- }
- }
-}
-
static const __DRItexBufferExtension intelTexBufferExtension = {
.base = { __DRI_TEX_BUFFER, 3 },
brw->need_flush_throttle = true;
intel_batchbuffer_flush(brw);
-
- if (INTEL_DEBUG & DEBUG_AUB) {
- aub_dump_bmp(ctx);
- }
}
/**
{ __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
+ { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } },
+
{ __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
+ { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } },
+
{ __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
return revision;
}
-/* Drop when RS headers get pulled to libdrm */
-#ifndef I915_PARAM_HAS_RESOURCE_STREAMER
-#define I915_PARAM_HAS_RESOURCE_STREAMER 36
-#endif
-
static void
shader_debug_log_mesa(void *data, const char *fmt, ...)
{
fprintf(stderr,
"\nERROR! DRI2 loader with getBuffersWithFormat() "
"support required\n");
- return false;
+ return NULL;
}
/* Allocate the private area */
screen = rzalloc(NULL, struct intel_screen);
if (!screen) {
fprintf(stderr, "\nERROR! Allocating private area failed\n");
- return false;
+ return NULL;
}
/* parse information in __driConfigOptions */
driParseOptionInfo(&screen->optionCache, brw_config_options.xml);
dri_screen->driverPrivate = (void *) screen;
if (!intel_init_bufmgr(screen))
- return false;
+ return NULL;
screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr);
if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
- return false;
+ return NULL;
+
+ const struct gen_device_info *devinfo = &screen->devinfo;
brw_process_intel_debug_variable();
if (INTEL_DEBUG & DEBUG_BUFMGR)
dri_bufmgr_set_debug(screen->bufmgr, true);
- if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo.gen < 7) {
+ if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
fprintf(stderr,
"shader_time debugging requires gen7 (Ivybridge) or better.\n");
INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
}
- if (INTEL_DEBUG & DEBUG_AUB)
- drm_intel_bufmgr_gem_set_aub_dump(screen->bufmgr, true);
-
-#ifndef I915_PARAM_MMAP_GTT_VERSION
-#define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
-#endif
if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
/* Theorectically unlimited! At least for individual objects...
*
screen->hw_has_timestamp = intel_detect_timestamp(screen);
/* GENs prior to 8 do not support EU/Subslice info */
- if (screen->devinfo.gen >= 8) {
+ if (devinfo->gen >= 8) {
intel_detect_sseu(screen);
- } else if (screen->devinfo.gen == 7) {
- screen->subslice_total = 1 << (screen->devinfo.gt - 1);
+ } else if (devinfo->gen == 7) {
+ screen->subslice_total = 1 << (devinfo->gt - 1);
}
if (intel_detect_pipelined_so(screen))
*
* Don't even try on pre-Gen6, since we don't attempt to use contexts there.
*/
- if (screen->devinfo.gen >= 6) {
+ if (devinfo->gen >= 6) {
struct drm_i915_reset_stats stats;
memset(&stats, 0, sizeof(stats));
screen->cmd_parser_version = 0;
}
- if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 2)
+ if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2)
screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
/* Haswell requires command parser version 4 in order to have L3
* atomic scratch1 and chicken3 bits
*/
- if (screen->devinfo.is_haswell && screen->cmd_parser_version >= 4) {
+ if (devinfo->is_haswell && screen->cmd_parser_version >= 4) {
screen->kernel_features |=
KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
}
* MI_MATH GPR registers, and version 7 in order to use
* MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
*/
- if (screen->devinfo.gen >= 8 ||
- (screen->devinfo.is_haswell && screen->cmd_parser_version >= 7)) {
+ if (devinfo->gen >= 8 ||
+ (devinfo->is_haswell && screen->cmd_parser_version >= 7)) {
screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
}
/* Gen7 needs at least command parser version 5 to support compute */
- if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 5)
+ if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
dri_screen->extensions = !screen->has_context_reset_notification
? screenExtensions : intelRobustScreenExtensions;
- screen->compiler = brw_compiler_create(screen,
- &screen->devinfo);
+ screen->compiler = brw_compiler_create(screen, devinfo);
screen->compiler->shader_debug_log = shader_debug_log_mesa;
screen->compiler->shader_perf_log = shader_perf_log_mesa;
screen->program_id = 1;
- if (screen->devinfo.has_resource_streamer) {
- screen->has_resource_streamer =
- intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER);
- }
+ screen->has_exec_fence =
+ intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
}
projects / mesa.git / blobdiff