* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <drm_fourcc.h>
+#include "drm-uapi/drm_fourcc.h"
#include <errno.h>
#include <time.h>
#include <unistd.h>
#include "main/hash.h"
#include "main/fbobject.h"
#include "main/version.h"
+#include "main/glthread.h"
#include "swrast/s_renderbuffer.h"
#include "util/ralloc.h"
+#include "util/disk_cache.h"
#include "brw_defines.h"
#include "brw_state.h"
#include "compiler/nir/nir.h"
#include "utils.h"
+#include "util/disk_cache.h"
#include "util/xmlpool.h"
-#ifndef DRM_FORMAT_MOD_INVALID
-#define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
-#endif
-
-#ifndef DRM_FORMAT_MOD_LINEAR
-#define DRM_FORMAT_MOD_LINEAR 0
-#endif
+#include "common/gen_defines.h"
static const __DRIconfigOptionsExtension brw_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
DRI_CONF_DESC_END
DRI_CONF_OPT_END
DRI_CONF_MESA_NO_ERROR("false")
+ DRI_CONF_MESA_GLTHREAD("false")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
- DRI_CONF_FORCE_S3TC_ENABLE("false")
-
DRI_CONF_PRECISE_TRIG("false")
DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST("false")
DRI_CONF_ALWAYS_FLUSH_BATCH("false")
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
DRI_CONF_DISABLE_THROTTLING("false")
DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
+ DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
DRI_CONF_SECTION_MISCELLANEOUS
DRI_CONF_GLSL_ZERO_INIT("false")
+ DRI_CONF_ALLOW_RGB10_CONFIGS("false")
+ DRI_CONF_ALLOW_RGB565_CONFIGS("true")
DRI_CONF_SECTION_END
DRI_CONF_END
};
#include "brw_context.h"
-#include "i915_drm.h"
+#include "drm-uapi/i915_drm.h"
/**
* For debugging purposes, this returns a time in seconds.
.setTexBuffer = intelSetTexBuffer,
.setTexBuffer2 = intelSetTexBuffer2,
- .releaseTexBuffer = NULL,
+ .releaseTexBuffer = intelReleaseTexBuffer,
};
static void
struct gl_context *ctx = &brw->ctx;
+ _mesa_glthread_finish(ctx);
+
FLUSH_VERTICES(ctx, 0);
if (flags & __DRI2_FLUSH_DRAWABLE)
};
static const struct intel_image_format intel_image_formats[] = {
+ { __DRI_IMAGE_FOURCC_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } },
+
{ __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+ { __DRI_IMAGE_FOURCC_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
{ __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+ { __DRI_IMAGE_FOURCC_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } },
+
/* For YUYV and UYVY buffers, we set up two overlapping DRI images
* and treat them as planar buffers in the compositors.
* Plane 0 is GR88 and samples YU or YV pairs and places Y into
{ .modifier = DRM_FORMAT_MOD_LINEAR , .since_gen = 1 },
{ .modifier = I915_FORMAT_MOD_X_TILED , .since_gen = 1 },
{ .modifier = I915_FORMAT_MOD_Y_TILED , .since_gen = 6 },
+ { .modifier = I915_FORMAT_MOD_Y_TILED_CCS , .since_gen = 9 },
};
static bool
modifier_is_supported(const struct gen_device_info *devinfo,
+ const struct intel_image_format *fmt, int dri_format,
uint64_t modifier)
{
+ const struct isl_drm_modifier_info *modinfo =
+ isl_drm_modifier_get_info(modifier);
int i;
+ /* ISL had better know about the modifier */
+ if (!modinfo)
+ return false;
+
+ if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
+ if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
+ return false;
+
+ /* CCS_E is not supported for planar images */
+ if (fmt && fmt->nplanes > 1)
+ return false;
+
+ if (fmt) {
+ assert(dri_format == 0);
+ dri_format = fmt->planes[0].dri_format;
+ }
+
+ mesa_format format = driImageFormatToGLFormat(dri_format);
+ /* Whether or not we support compression is based on the RGBA non-sRGB
+ * version of the format.
+ */
+ format = _mesa_format_fallback_rgbx_to_rgba(format);
+ format = _mesa_get_srgb_format_linear(format);
+ if (!isl_format_supports_ccs_e(devinfo,
+ brw_isl_format_for_mesa_format(format)))
+ return false;
+ }
+
for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
if (supported_modifiers[i].modifier != modifier)
continue;
static const struct intel_image_format *
intel_image_format_lookup(int fourcc)
{
- const struct intel_image_format *f = NULL;
-
for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
- if (intel_image_formats[i].fourcc == fourcc) {
- f = &intel_image_formats[i];
- break;
- }
+ if (intel_image_formats[i].fourcc == fourcc)
+ return &intel_image_formats[i];
}
- return f;
+ return NULL;
}
-static boolean intel_lookup_fourcc(int dri_format, int *fourcc)
+static boolean
+intel_image_get_fourcc(__DRIimage *image, int *fourcc)
{
+ if (image->planar_format) {
+ *fourcc = image->planar_format->fourcc;
+ return true;
+ }
+
for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
- if (intel_image_formats[i].planes[0].dri_format == dri_format) {
+ if (intel_image_formats[i].planes[0].dri_format == image->dri_format) {
*fourcc = intel_image_formats[i].fourcc;
return true;
}
level - mt->first_level);
image->height = minify(mt->surf.phys_level0_sa.height,
level - mt->first_level);
- image->pitch = mt->surf.row_pitch;
+ image->pitch = mt->surf.row_pitch_B;
image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
&image->tile_x,
brw_bo_reference(irb->mt->bo);
image->width = rb->Width;
image->height = rb->Height;
- image->pitch = irb->mt->surf.row_pitch;
+ image->pitch = irb->mt->surf.row_pitch_B;
image->dri_format = driGLFormatToImageFormat(image->format);
image->has_depthstencil = irb->mt->stencil_mt? true : false;
intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset);
image->dri_format = driGLFormatToImageFormat(image->format);
image->has_depthstencil = iobj->mt->stencil_mt? true : false;
- if (image->dri_format == MESA_FORMAT_NONE) {
+ image->planar_format = iobj->planar_format;
+ if (image->dri_format == __DRI_IMAGE_FORMAT_NONE) {
*error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
free(image);
return NULL;
MODIFIER_PRIORITY_LINEAR,
MODIFIER_PRIORITY_X,
MODIFIER_PRIORITY_Y,
+ MODIFIER_PRIORITY_Y_CCS,
};
const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
+ [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
};
static uint64_t
select_best_modifier(struct gen_device_info *devinfo,
+ int dri_format,
const uint64_t *modifiers,
const unsigned count)
{
enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
for (int i = 0; i < count; i++) {
- if (!modifier_is_supported(devinfo, modifiers[i]))
+ if (!modifier_is_supported(devinfo, NULL, dri_format, modifiers[i]))
continue;
switch (modifiers[i]) {
+ case I915_FORMAT_MOD_Y_TILED_CCS:
+ prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
+ break;
case I915_FORMAT_MOD_Y_TILED:
prio = MAX2(prio, MODIFIER_PRIORITY_Y);
break;
if (modifier == DRM_FORMAT_MOD_INVALID) {
if (modifiers) {
/* User requested specific modifiers */
- modifier = select_best_modifier(&screen->devinfo, modifiers, count);
+ modifier = select_best_modifier(&screen->devinfo, format,
+ modifiers, count);
if (modifier == DRM_FORMAT_MOD_INVALID)
return NULL;
} else {
return NULL;
}
- /* We request that the bufmgr zero because, if a buffer gets re-used from
- * the pool, we don't want to leak random garbage from our process to some
- * other.
+ struct isl_surf aux_surf;
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 0);
+ if (!ok) {
+ free(image);
+ return NULL;
+ }
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
+ aux_surf.size_B = 0;
+ }
+
+ /* We request that the bufmgr zero the buffer for us for two reasons:
+ *
+ * 1) If a buffer gets re-used from the pool, we don't want to leak random
+ * garbage from our process to some other.
+ *
+ * 2) For images with CCS_E, we want to ensure that the CCS starts off in
+ * a valid state. A CCS value of 0 indicates that the given block is
+ * in the pass-through state which is what we want.
*/
- image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", surf.size,
+ image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
+ surf.size_B + aux_surf.size_B,
+ BRW_MEMZONE_OTHER,
isl_tiling_to_i915_tiling(mod_info->tiling),
- surf.row_pitch, BO_ALLOC_ZEROED);
+ surf.row_pitch_B, BO_ALLOC_ZEROED);
if (image->bo == NULL) {
free(image);
return NULL;
}
image->width = width;
image->height = height;
- image->pitch = surf.row_pitch;
+ image->pitch = surf.row_pitch_B;
image->modifier = modifier;
+ if (aux_surf.size_B) {
+ image->aux_offset = surf.size_B;
+ image->aux_pitch = aux_surf.row_pitch_B;
+ image->aux_size = aux_surf.size_B;
+ }
+
return image;
}
loaderPrivate);
}
+static void *
+intel_map_image(__DRIcontext *context, __DRIimage *image,
+ int x0, int y0, int width, int height,
+ unsigned int flags, int *stride, void **map_info)
+{
+ struct brw_context *brw = NULL;
+ struct brw_bo *bo = NULL;
+ void *raw_data = NULL;
+ GLuint pix_w = 1;
+ GLuint pix_h = 1;
+ GLint pix_bytes = 1;
+
+ if (!context || !image || !stride || !map_info || *map_info)
+ return NULL;
+
+ if (x0 < 0 || x0 >= image->width || width > image->width - x0)
+ return NULL;
+
+ if (y0 < 0 || y0 >= image->height || height > image->height - y0)
+ return NULL;
+
+ if (flags & MAP_INTERNAL_MASK)
+ return NULL;
+
+ brw = context->driverPrivate;
+ bo = image->bo;
+
+ assert(brw);
+ assert(bo);
+
+ /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
+ raw_data = brw_bo_map(brw, bo, flags);
+ if (!raw_data)
+ return NULL;
+
+ _mesa_get_format_block_size(image->format, &pix_w, &pix_h);
+ pix_bytes = _mesa_get_format_bytes(image->format);
+
+ assert(pix_w);
+ assert(pix_h);
+ assert(pix_bytes > 0);
+
+ raw_data += (x0 / pix_w) * pix_bytes + (y0 / pix_h) * image->pitch;
+
+ brw_bo_reference(bo);
+
+ *stride = image->pitch;
+ *map_info = bo;
+
+ return raw_data;
+}
+
+static void
+intel_unmap_image(__DRIcontext *context, __DRIimage *image, void *map_info)
+{
+ struct brw_bo *bo = map_info;
+
+ brw_bo_unmap(bo);
+ brw_bo_unreference(bo);
+}
+
static __DRIimage *
intel_create_image_with_modifiers(__DRIscreen *dri_screen,
int width, int height, int format,
*value = image->pitch;
return true;
case __DRI_IMAGE_ATTRIB_HANDLE:
- *value = image->bo->gem_handle;
+ *value = brw_bo_export_gem_handle(image->bo);
return true;
case __DRI_IMAGE_ATTRIB_NAME:
return !brw_bo_flink(image->bo, (uint32_t *) value);
case __DRI_IMAGE_ATTRIB_FD:
return !brw_bo_gem_export_to_prime(image->bo, value);
case __DRI_IMAGE_ATTRIB_FOURCC:
- return intel_lookup_fourcc(image->dri_format, value);
+ return intel_image_get_fourcc(image, value);
case __DRI_IMAGE_ATTRIB_NUM_PLANES:
- *value = 1;
+ if (isl_drm_modifier_has_aux(image->modifier)) {
+ assert(!image->planar_format || image->planar_format->nplanes == 1);
+ *value = 2;
+ } else if (image->planar_format) {
+ *value = image->planar_format->nplanes;
+ } else {
+ *value = 1;
+ }
return true;
case __DRI_IMAGE_ATTRIB_OFFSET:
*value = image->offset;
}
}
+static GLboolean
+intel_query_format_modifier_attribs(__DRIscreen *dri_screen,
+ uint32_t fourcc, uint64_t modifier,
+ int attrib, uint64_t *value)
+{
+ struct intel_screen *screen = dri_screen->driverPrivate;
+ const struct intel_image_format *f = intel_image_format_lookup(fourcc);
+
+ if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
+ return false;
+
+ switch (attrib) {
+ case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT:
+ *value = isl_drm_modifier_has_aux(modifier) ? 2 : f->nplanes;
+ return true;
+
+ default:
+ return false;
+ }
+}
+
static __DRIimage *
intel_dup_image(__DRIimage *orig_image, void *loaderPrivate)
{
image->tile_y = orig_image->tile_y;
image->has_depthstencil = orig_image->has_depthstencil;
image->data = loaderPrivate;
+ image->aux_offset = orig_image->aux_offset;
+ image->aux_pitch = orig_image->aux_pitch;
memcpy(image->strides, orig_image->strides, sizeof(image->strides));
memcpy(image->offsets, orig_image->offsets, sizeof(image->offsets));
return NULL;
if (modifier != DRM_FORMAT_MOD_INVALID &&
- !modifier_is_supported(&screen->devinfo, modifier))
+ !modifier_is_supported(&screen->devinfo, f, 0, modifier))
return NULL;
if (f->nplanes == 1)
image->planar_format = f;
- image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]);
+ if (modifier != DRM_FORMAT_MOD_INVALID) {
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(modifier);
+ uint32_t tiling = isl_tiling_to_i915_tiling(mod_info->tiling);
+ image->bo = brw_bo_gem_create_from_prime_tiled(screen->bufmgr, fds[0],
+ tiling, strides[0]);
+ } else {
+ image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]);
+ }
+
if (image->bo == NULL) {
free(image);
return NULL;
else
image->modifier = tiling_to_modifier(image->bo->tiling_mode);
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->modifier);
+
int size = 0;
+ struct isl_surf surf;
for (i = 0; i < f->nplanes; i++) {
index = f->planes[i].buffer_index;
image->offsets[index] = offsets[index];
image->strides[index] = strides[index];
- const struct isl_drm_modifier_info *mod_info =
- isl_drm_modifier_get_info(image->modifier);
-
mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
+ /* The images we will create are actually based on the RGBA non-sRGB
+ * version of the format.
+ */
+ format = _mesa_format_fallback_rgbx_to_rgba(format);
+ format = _mesa_get_srgb_format_linear(format);
- struct isl_surf surf;
ok = isl_surf_init(&screen->isl_dev, &surf,
.dim = ISL_SURF_DIM_2D,
.format = brw_isl_format_for_mesa_format(format),
.levels = 1,
.array_len = 1,
.samples = 1,
- .row_pitch = strides[index],
+ .row_pitch_B = strides[index],
.usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_TEXTURE_BIT |
ISL_SURF_USAGE_STORAGE_BIT,
return NULL;
}
- const int end = offsets[index] + surf.size;
+ const int end = offsets[index] + surf.size_B;
+ if (size < end)
+ size = end;
+ }
+
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
+ /* Even though we initialize surf in the loop above, we know that
+ * anything with CCS_E will have exactly one plane so surf is properly
+ * initialized when we get here.
+ */
+ assert(f->nplanes == 1);
+
+ image->aux_offset = offsets[1];
+ image->aux_pitch = strides[1];
+
+ /* Scanout hardware requires that the CCS be placed after the main
+ * surface in memory. We consider any CCS that is placed any earlier in
+ * memory to be invalid and reject it.
+ *
+ * At some point in the future, this restriction may be relaxed if the
+ * hardware becomes less strict but we may need a new modifier for that.
+ */
+ assert(size > 0);
+ if (image->aux_offset < size) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+ }
+
+ struct isl_surf aux_surf;
+ ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf,
+ image->aux_pitch);
+ if (!ok) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+ }
+
+ image->aux_size = aux_surf.size_B;
+
+ const int end = image->aux_offset + aux_surf.size_B;
if (size < end)
size = end;
+ } else {
+ assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
}
/* Check that the requested image actually fits within the BO. 'size'
return NULL;
}
- image->dma_buf_imported = true;
image->yuv_color_space = yuv_color_space;
image->sample_range = sample_range;
image->horizontal_siting = horizontal_siting;
loaderPrivate);
}
+static bool
+intel_image_format_is_supported(const struct gen_device_info *devinfo,
+ const struct intel_image_format *fmt)
+{
+ /* Currently, all formats with an intel_image_format are available on all
+ * platforms so there's really nothing to check there.
+ */
+
+#ifndef NDEBUG
+ if (fmt->nplanes == 1) {
+ mesa_format format = driImageFormatToGLFormat(fmt->planes[0].dri_format);
+ /* The images we will create are actually based on the RGBA non-sRGB
+ * version of the format.
+ */
+ format = _mesa_format_fallback_rgbx_to_rgba(format);
+ format = _mesa_get_srgb_format_linear(format);
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
+ assert(isl_format_supports_rendering(devinfo, isl_format));
+ }
+#endif
+
+ return true;
+}
+
static GLboolean
-intel_query_dma_buf_formats(__DRIscreen *screen, int max,
+intel_query_dma_buf_formats(__DRIscreen *_screen, int max,
int *formats, int *count)
{
- int i, j = 0;
+ struct intel_screen *screen = _screen->driverPrivate;
+ int num_formats = 0, i;
- if (max == 0) {
- *count = ARRAY_SIZE(intel_image_formats) - 1; /* not SARGB */
- return true;
- }
+ for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
+ /* These two formats are valid DRI formats but do not exist in
+ * drm_fourcc.h in the Linux kernel. We don't want to accidentally
+ * advertise them through the EGL layer.
+ */
+ if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 ||
+ intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888)
+ continue;
- for (i = 0; i < (ARRAY_SIZE(intel_image_formats)) && j < max; i++) {
- if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888)
- continue;
- formats[j++] = intel_image_formats[i].fourcc;
+ if (!intel_image_format_is_supported(&screen->devinfo,
+ &intel_image_formats[i]))
+ continue;
+
+ num_formats++;
+ if (max == 0)
+ continue;
+
+ formats[num_formats - 1] = intel_image_formats[i].fourcc;
+ if (num_formats >= max)
+ break;
}
- *count = j;
+ *count = num_formats;
return true;
}
if (f == NULL)
return false;
+ if (!intel_image_format_is_supported(&screen->devinfo, f))
+ return false;
+
for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
uint64_t modifier = supported_modifiers[i].modifier;
- if (!modifier_is_supported(&screen->devinfo, modifier))
+ if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
continue;
num_mods++;
for (i = 0; i < num_mods && i < max; i++) {
if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
- f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) {
+ f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV ||
+ f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) {
external_only[i] = GL_TRUE;
}
else {
static __DRIimage *
intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
{
- int width, height, offset, stride, dri_format, index;
- const struct intel_image_format *f;
+ int width, height, offset, stride, size, dri_format;
__DRIimage *image;
- if (parent == NULL || parent->planar_format == NULL)
- return NULL;
-
- f = parent->planar_format;
+ if (parent == NULL)
+ return NULL;
- if (plane >= f->nplanes)
- return NULL;
+ width = parent->width;
+ height = parent->height;
+
+ const struct intel_image_format *f = parent->planar_format;
+
+ if (f && plane < f->nplanes) {
+ /* Use the planar format definition. */
+ width >>= f->planes[plane].width_shift;
+ height >>= f->planes[plane].height_shift;
+ dri_format = f->planes[plane].dri_format;
+ int index = f->planes[plane].buffer_index;
+ offset = parent->offsets[index];
+ stride = parent->strides[index];
+ size = height * stride;
+ } else if (plane == 0) {
+ /* The only plane of a non-planar image: copy the parent definition
+ * directly. */
+ dri_format = parent->dri_format;
+ offset = parent->offset;
+ stride = parent->pitch;
+ size = height * stride;
+ } else if (plane == 1 && parent->modifier != DRM_FORMAT_MOD_INVALID &&
+ isl_drm_modifier_has_aux(parent->modifier)) {
+ /* Auxiliary plane */
+ dri_format = parent->dri_format;
+ offset = parent->aux_offset;
+ stride = parent->aux_pitch;
+ size = parent->aux_size;
+ } else {
+ return NULL;
+ }
- width = parent->width >> f->planes[plane].width_shift;
- height = parent->height >> f->planes[plane].height_shift;
- dri_format = f->planes[plane].dri_format;
- index = f->planes[plane].buffer_index;
- offset = parent->offsets[index];
- stride = parent->strides[index];
+ if (offset + size > parent->bo->size) {
+ _mesa_warning(NULL, "intel_from_planar: subimage out of bounds");
+ return NULL;
+ }
image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
if (image == NULL)
return NULL;
- if (offset + height * stride > parent->bo->size) {
- _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
- free(image);
- return NULL;
- }
-
image->bo = parent->bo;
brw_bo_reference(parent->bo);
image->modifier = parent->modifier;
}
static const __DRIimageExtension intelImageExtension = {
- .base = { __DRI_IMAGE, 15 },
+ .base = { __DRI_IMAGE, 16 },
.createImageFromName = intel_create_image_from_name,
.createImageFromRenderbuffer = intel_create_image_from_renderbuffer,
.createImageFromDmaBufs = intel_create_image_from_dma_bufs,
.blitImage = NULL,
.getCapabilities = NULL,
- .mapImage = NULL,
- .unmapImage = NULL,
+ .mapImage = intel_map_image,
+ .unmapImage = intel_unmap_image,
.createImageWithModifiers = intel_create_image_with_modifiers,
.createImageFromDmaBufs2 = intel_create_image_from_dma_bufs2,
.queryDmaBufFormats = intel_query_dma_buf_formats,
.queryDmaBufModifiers = intel_query_dma_buf_modifiers,
+ .queryDmaBufFormatModifierAttribs = intel_query_format_modifier_attribs,
};
static uint64_t
case __DRI2_RENDERER_HAS_TEXTURE_3D:
value[0] = 1;
return 0;
+ case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
+ value[0] = 0;
+ if (brw_hw_context_set_priority(screen->bufmgr,
+ 0, GEN_CONTEXT_HIGH_PRIORITY) == 0)
+ value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
+ if (brw_hw_context_set_priority(screen->bufmgr,
+ 0, GEN_CONTEXT_LOW_PRIORITY) == 0)
+ value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
+ /* reset to default last, just in case */
+ if (brw_hw_context_set_priority(screen->bufmgr,
+ 0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0)
+ value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
+ return 0;
+ case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB:
+ value[0] = 1;
+ return 0;
default:
return driQueryRendererIntegerCommon(dri_screen, param, value);
}
return -1;
}
+static void
+brw_set_cache_funcs(__DRIscreen *dri_screen,
+ __DRIblobCacheSet set, __DRIblobCacheGet get)
+{
+ const struct intel_screen *const screen =
+ (struct intel_screen *) dri_screen->driverPrivate;
+
+ if (!screen->disk_cache)
+ return;
+
+ disk_cache_set_callbacks(screen->disk_cache, set, get);
+}
+
static const __DRI2rendererQueryExtension intelRendererQueryExtension = {
.base = { __DRI2_RENDERER_QUERY, 1 },
.base = { __DRI2_ROBUSTNESS, 1 }
};
+static const __DRI2blobExtension intelBlobExtension = {
+ .base = { __DRI2_BLOB, 1 },
+ .set_cache_funcs = brw_set_cache_funcs
+};
+
+static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension = {
+ .base = { __DRI_MUTABLE_RENDER_BUFFER_DRIVER, 1 },
+};
+
static const __DRIextension *screenExtensions[] = {
&intelTexBufferExtension.base,
&intelFenceExtension.base,
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
+ &intelMutableRenderBufferExtension.base,
&dri2ConfigQueryExtension.base,
&dri2NoErrorExtension.base,
+ &intelBlobExtension.base,
NULL
};
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
+ &intelMutableRenderBufferExtension.base,
&dri2ConfigQueryExtension.base,
&dri2Robustness.base,
&dri2NoErrorExtension.base,
+ &intelBlobExtension.base,
NULL
};
brw_bufmgr_destroy(screen->bufmgr);
driDestroyOptionInfo(&screen->optionCache);
+ disk_cache_destroy(screen->disk_cache);
+
ralloc_free(screen);
sPriv->driverPrivate = NULL;
}
fb->Visual.samples = num_samples;
}
- if (mesaVis->redBits == 5) {
+ if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) {
+ rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
+ : MESA_FORMAT_R10G10B10A2_UNORM;
+ } else if (mesaVis->redBits == 10) {
+ rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
+ : MESA_FORMAT_R10G10B10X2_UNORM;
+ } else if (mesaVis->redBits == 5) {
rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
: MESA_FORMAT_B5G6R5_UNORM;
} else if (mesaVis->sRGBCapable) {
fb->Visual.sRGBCapable = true;
}
+ /* mesaVis->sRGBCapable was set, user is asking for sRGB */
+ bool srgb_cap_set = mesaVis->redBits >= 8 && mesaVis->sRGBCapable;
+
/* setup the hardware-based renderbuffers */
rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
_mesa_attach_and_own_rb(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
+ rb->need_srgb = srgb_cap_set;
if (mesaVis->doubleBufferMode) {
rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
_mesa_attach_and_own_rb(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
+ rb->need_srgb = srgb_cap_set;
}
/*
_mesa_reference_framebuffer(&fb, NULL);
}
+static void
+intel_cs_timestamp_frequency(struct intel_screen *screen)
+{
+ /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
+ * gen10, PCI-id is enough to figure it out.
+ */
+ assert(screen->devinfo.gen >= 10);
+
+ int ret, freq;
+
+ ret = intel_get_param(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ &freq);
+ if (ret < 0) {
+ _mesa_warning(NULL,
+ "Kernel 4.15 required to read the CS timestamp frequency.\n");
+ return;
+ }
+
+ screen->devinfo.timestamp_frequency = freq;
+}
+
static void
intel_detect_sseu(struct intel_screen *screen)
{
if (getenv("INTEL_NO_HW") != NULL)
screen->no_hw = true;
- screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd, BATCH_SZ);
+ screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd);
if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
return false;
}
- if (!intel_get_boolean(screen, I915_PARAM_HAS_WAIT_TIMEOUT)) {
- fprintf(stderr, "[%s: %u] Kernel 3.6 required.\n", __func__, __LINE__);
+ if (!intel_get_boolean(screen, I915_PARAM_HAS_EXEC_NO_RELOC)) {
+ fprintf(stderr, "[%s: %u] Kernel 3.9 required.\n", __func__, __LINE__);
return false;
}
static bool
intel_detect_swizzling(struct intel_screen *screen)
{
- struct brw_bo *buffer;
- unsigned flags = 0;
- uint32_t aligned_pitch;
+ /* Broadwell PRM says:
+ *
+ * "Before Gen8, there was a historical configuration control field to
+ * swizzle address bit[6] for in X/Y tiling modes. This was set in three
+ * different places: TILECTL[1:0], ARB_MODE[5:4], and
+ * DISP_ARB_CTL[14:13].
+ *
+ * For Gen8 and subsequent generations, the swizzle fields are all
+ * reserved, and the CPU's memory controller performs all address
+ * swizzling modifications."
+ */
+ if (screen->devinfo.gen >= 8)
+ return false;
+
uint32_t tiling = I915_TILING_X;
uint32_t swizzle_mode = 0;
-
- buffer = brw_bo_alloc_tiled_2d(screen->bufmgr, "swizzle test",
- 64, 64, 4, tiling, &aligned_pitch, flags);
+ struct brw_bo *buffer =
+ brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
+ BRW_MEMZONE_OTHER, tiling, 512, 0);
if (buffer == NULL)
return false;
brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
brw_bo_unreference(buffer);
- if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE)
- return false;
- else
- return true;
+ return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
}
static int
bool success = false;
/* Create a zero'ed temporary buffer for reading our results */
- results = brw_bo_alloc(screen->bufmgr, "registers", 4096, 0);
+ results = brw_bo_alloc(screen->bufmgr, "registers", 4096, BRW_MEMZONE_OTHER);
if (results == NULL)
goto err;
- bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, 0);
+ bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, BRW_MEMZONE_OTHER);
if (bo == NULL)
goto err_results;
}
}
+static unsigned
+intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap)
+{
+ if (dri_screen->dri2.loader && dri_screen->dri2.loader->base.version >= 4 &&
+ dri_screen->dri2.loader->getCapability)
+ return dri_screen->dri2.loader->getCapability(dri_screen->loaderPrivate, cap);
+
+ if (dri_screen->image.loader && dri_screen->image.loader->base.version >= 2 &&
+ dri_screen->image.loader->getCapability)
+ return dri_screen->image.loader->getCapability(dri_screen->loaderPrivate, cap);
+
+ return 0;
+}
+
static __DRIconfig**
intel_screen_make_configs(__DRIscreen *dri_screen)
{
MESA_FORMAT_B8G8R8A8_UNORM,
MESA_FORMAT_B8G8R8X8_UNORM,
+ MESA_FORMAT_B8G8R8A8_SRGB,
+
+ /* For 10 bpc, 30 bit depth framebuffers. */
+ MESA_FORMAT_B10G10R10A2_UNORM,
+ MESA_FORMAT_B10G10R10X2_UNORM,
+
/* The 32-bit RGBA format must not precede the 32-bit BGRA format.
* Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
* server may disagree on which format the GLXFBConfig represents,
/* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
MESA_FORMAT_R8G8B8X8_UNORM,
+
+ MESA_FORMAT_R8G8B8A8_SRGB,
};
- /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
+ /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
static const GLenum back_buffer_modes[] = {
- GLX_SWAP_UNDEFINED_OML, GLX_NONE,
+ __DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE
};
static const uint8_t singlesample_samples[1] = {0};
- static const uint8_t multisample_samples[2] = {4, 8};
struct intel_screen *screen = dri_screen->driverPrivate;
const struct gen_device_info *devinfo = &screen->devinfo;
uint8_t depth_bits[4], stencil_bits[4];
__DRIconfig **configs = NULL;
- /* Generate singlesample configs without accumulation buffer. */
- for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) {
+ /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
+ unsigned num_formats;
+ if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING))
+ num_formats = ARRAY_SIZE(formats);
+ else
+ num_formats = ARRAY_SIZE(formats) - 3; /* all - RGBA_ORDERING formats */
+
+ /* Shall we expose 10 bpc formats? */
+ bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache,
+ "allow_rgb10_configs");
+ /* Shall we expose 565 formats? */
+ bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache,
+ "allow_rgb565_configs");
+
+ /* Generate singlesample configs, each without accumulation buffer
+ * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
+ */
+ for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
int num_depth_stencil_bits = 2;
+ if (!allow_rgb10_configs &&
+ (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+ formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
+ if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM)
+ continue;
+
/* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
* buffer that has a different number of bits per pixel than the color
* buffer, gen >= 6 supports this.
num_depth_stencil_bits,
back_buffer_modes, 2,
singlesample_samples, 1,
- false, false);
+ false, false,
+ /*mutable_render_buffer*/ true);
configs = driConcatConfigs(configs, new_configs);
}
/* Generate the minimum possible set of configs that include an
* accumulation buffer.
*/
- for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) {
+ for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
+ if (!allow_rgb10_configs &&
+ (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+ formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
+ if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM)
+ continue;
+
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
depth_bits[0] = 16;
stencil_bits[0] = 0;
depth_bits, stencil_bits, 1,
back_buffer_modes, 1,
singlesample_samples, 1,
- true, false);
+ true, false, false);
configs = driConcatConfigs(configs, new_configs);
}
* supported. Singlebuffer configs are not supported because no one wants
* them.
*/
- for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) {
+ for (unsigned i = 0; i < num_formats; i++) {
if (devinfo->gen < 6)
break;
+ if (!allow_rgb10_configs &&
+ (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+ formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
+ if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM)
+ continue;
+
__DRIconfig **new_configs;
const int num_depth_stencil_bits = 2;
int num_msaa_modes = 0;
+ const uint8_t *multisample_samples = NULL;
depth_bits[0] = 0;
stencil_bits[0] = 0;
stencil_bits[1] = 8;
}
- if (devinfo->gen >= 7)
- num_msaa_modes = 2;
- else if (devinfo->gen == 6)
- num_msaa_modes = 1;
+ if (devinfo->gen >= 9) {
+ static const uint8_t multisample_samples_gen9[] = {2, 4, 8, 16};
+ multisample_samples = multisample_samples_gen9;
+ num_msaa_modes = ARRAY_SIZE(multisample_samples_gen9);
+ } else if (devinfo->gen == 8) {
+ static const uint8_t multisample_samples_gen8[] = {2, 4, 8};
+ multisample_samples = multisample_samples_gen8;
+ num_msaa_modes = ARRAY_SIZE(multisample_samples_gen8);
+ } else if (devinfo->gen == 7) {
+ static const uint8_t multisample_samples_gen7[] = {4, 8};
+ multisample_samples = multisample_samples_gen7;
+ num_msaa_modes = ARRAY_SIZE(multisample_samples_gen7);
+ } else if (devinfo->gen == 6) {
+ static const uint8_t multisample_samples_gen6[] = {4};
+ multisample_samples = multisample_samples_gen6;
+ num_msaa_modes = ARRAY_SIZE(multisample_samples_gen6);
+ }
new_configs = driCreateConfigs(formats[i],
depth_bits,
back_buffer_modes, 1,
multisample_samples,
num_msaa_modes,
- false, false);
+ false, false, false);
configs = driConcatConfigs(configs, new_configs);
}
const bool has_astc = screen->devinfo.gen >= 9;
switch (screen->devinfo.gen) {
+ case 11:
case 10:
case 9:
case 8:
/**
* Return the revision (generally the revid field of the PCI header) of the
* graphics device.
- *
- * XXX: This function is useful to keep around even if it is not currently in
- * use. It is necessary for new platforms and revision specific workarounds or
- * features. Please don't remove it so that we know it at least continues to
- * build.
*/
-static __attribute__((__unused__)) int
-brw_get_revision(int fd)
+static int
+intel_device_get_revision(int fd)
{
struct drm_i915_getparam gp;
int revision;
va_start(args, fmt);
GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_OTHER,
- MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
+ _mesa_gl_vdebugf(&brw->ctx, &msg_id,
+ MESA_DEBUG_SOURCE_SHADER_COMPILER,
+ MESA_DEBUG_TYPE_OTHER,
+ MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
va_end(args);
}
if (brw->perf_debug) {
GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_PERFORMANCE,
- MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
+ _mesa_gl_vdebugf(&brw->ctx, &msg_id,
+ MESA_DEBUG_SOURCE_SHADER_COMPILER,
+ MESA_DEBUG_TYPE_PERFORMANCE,
+ MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
}
va_end(args);
}
-static int
-parse_devid_override(const char *devid_override)
-{
- static const struct {
- const char *name;
- int pci_id;
- } name_map[] = {
- { "brw", 0x2a02 },
- { "g4x", 0x2a42 },
- { "ilk", 0x0042 },
- { "snb", 0x0126 },
- { "ivb", 0x016a },
- { "hsw", 0x0d2e },
- { "byt", 0x0f33 },
- { "bdw", 0x162e },
- { "skl", 0x1912 },
- { "kbl", 0x5912 },
- { "cnl", 0x5a52 },
- };
-
- for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
- if (!strcmp(name_map[i].name, devid_override))
- return name_map[i].pci_id;
- }
-
- return strtol(devid_override, NULL, 0);
-}
-
-/**
- * Get the PCI ID for the device. This can be overridden by setting the
- * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
- *
- * Returns -1 on ioctl failure.
- */
-static int
-get_pci_device_id(struct intel_screen *screen)
-{
- if (geteuid() == getuid()) {
- char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
- if (devid_override) {
- screen->no_hw = true;
- return parse_devid_override(devid_override);
- }
- }
-
- return intel_get_integer(screen, I915_PARAM_CHIPSET_ID);
-}
-
/**
* This is the driver specific part of the createNewScreen entry point.
* Called when using DRI2.
return NULL;
}
/* parse information in __driConfigOptions */
- driParseOptionInfo(&screen->optionCache, brw_config_options.xml);
+ driOptionCache options;
+ memset(&options, 0, sizeof(options));
+
+ driParseOptionInfo(&options, brw_config_options.xml);
+ driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum,
+ "i965", NULL);
+ driDestroyOptionCache(&options);
screen->driScrnPriv = dri_screen;
dri_screen->driverPrivate = (void *) screen;
- screen->deviceID = get_pci_device_id(screen);
+ screen->deviceID = gen_get_pci_device_id_override();
+ if (screen->deviceID < 0)
+ screen->deviceID = intel_get_integer(screen, I915_PARAM_CHIPSET_ID);
+ else
+ screen->no_hw = true;
if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
return NULL;
+ screen->devinfo.revision = intel_device_get_revision(dri_screen->fd);
+
if (!intel_init_bufmgr(screen))
return NULL;
isl_device_init(&screen->isl_dev, &screen->devinfo,
screen->hw_has_swizzling);
+ if (devinfo->gen >= 10)
+ intel_cs_timestamp_frequency(screen);
+
/* GENs prior to 8 do not support EU/Subslice info */
if (devinfo->gen >= 8) {
intel_detect_sseu(screen);
}
/* Kernel 4.13 retuired for exec object capture */
-#ifndef I915_PARAM_HAS_EXEC_CAPTURE
-#define I915_PARAM_HAS_EXEC_CAPTURE 45
-#endif
if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_CAPTURE)) {
screen->kernel_features |= KERNEL_ALLOWS_EXEC_CAPTURE;
}
+ if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_BATCH_FIRST)) {
+ screen->kernel_features |= KERNEL_ALLOWS_EXEC_BATCH_FIRST;
+ }
+
if (!intel_detect_pipelined_so(screen)) {
/* We can't do anything, so the effective version is 0. */
screen->cmd_parser_version = 0;
if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
+ if (intel_get_boolean(screen, I915_PARAM_HAS_CONTEXT_ISOLATION))
+ screen->kernel_features |= KERNEL_ALLOWS_CONTEXT_ISOLATION;
+
const char *force_msaa = getenv("INTEL_FORCE_MSAA");
if (force_msaa) {
screen->winsys_msaa_samples_override =
screen->compiler = brw_compiler_create(screen, devinfo);
screen->compiler->shader_debug_log = shader_debug_log_mesa;
screen->compiler->shader_perf_log = shader_perf_log_mesa;
- screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8;
- screen->program_id = 1;
+
+ /* Changing the meaning of constant buffer pointers from a dynamic state
+ * offset to an absolute address is only safe if the kernel isolates other
+ * contexts from our changes.
+ */
+ screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8 ||
+ !(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION);
+
+ screen->compiler->supports_pull_constants = true;
screen->has_exec_fence =
intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
intel_screen_init_surface_formats(screen);
+ if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
+ unsigned int caps = intel_get_integer(screen, I915_PARAM_HAS_SCHEDULER);
+ if (caps) {
+ fprintf(stderr, "Kernel scheduler detected: %08x\n", caps);
+ if (caps & I915_SCHEDULER_CAP_PRIORITY)
+ fprintf(stderr, " - User priority sorting enabled\n");
+ if (caps & I915_SCHEDULER_CAP_PREEMPTION)
+ fprintf(stderr, " - Preemption enabled\n");
+ }
+ }
+
+ brw_disk_cache_init(screen);
+
return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
}
width,
height,
cpp,
+ BRW_MEMZONE_OTHER,
I915_TILING_X, &pitch,
- BO_ALLOC_FOR_RENDER);
+ BO_ALLOC_BUSY);
if (intelBuffer->bo == NULL) {
free(intelBuffer);
projects / mesa.git / blobdiff