* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <drm_fourcc.h>
+#include "drm-uapi/drm_fourcc.h"
#include <errno.h>
#include <time.h>
#include <unistd.h>
#include "main/hash.h"
#include "main/fbobject.h"
#include "main/version.h"
+#include "main/glthread.h"
#include "swrast/s_renderbuffer.h"
#include "util/ralloc.h"
#include "util/disk_cache.h"
DRI_CONF_DESC_END
DRI_CONF_OPT_END
DRI_CONF_MESA_NO_ERROR("false")
+ DRI_CONF_MESA_GLTHREAD("false")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST("false")
DRI_CONF_ALWAYS_FLUSH_BATCH("false")
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
DRI_CONF_DISABLE_THROTTLING("false")
DRI_CONF_SECTION_MISCELLANEOUS
DRI_CONF_GLSL_ZERO_INIT("false")
DRI_CONF_ALLOW_RGB10_CONFIGS("false")
+ DRI_CONF_ALLOW_RGB565_CONFIGS("true")
DRI_CONF_SECTION_END
DRI_CONF_END
};
#include "brw_context.h"
-#include "i915_drm.h"
+#include "drm-uapi/i915_drm.h"
/**
* For debugging purposes, this returns a time in seconds.
struct gl_context *ctx = &brw->ctx;
+ _mesa_glthread_finish(ctx);
+
FLUSH_VERTICES(ctx, 0);
if (flags & __DRI2_FLUSH_DRAWABLE)
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+ { __DRI_IMAGE_FOURCC_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
+
{ __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+ { __DRI_IMAGE_FOURCC_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } },
+
/* For YUYV and UYVY buffers, we set up two overlapping DRI images
* and treat them as planar buffers in the compositors.
* Plane 0 is GR88 and samples YU or YV pairs and places Y into
level - mt->first_level);
image->height = minify(mt->surf.phys_level0_sa.height,
level - mt->first_level);
- image->pitch = mt->surf.row_pitch;
+ image->pitch = mt->surf.row_pitch_B;
image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
&image->tile_x,
brw_bo_reference(irb->mt->bo);
image->width = rb->Width;
image->height = rb->Height;
- image->pitch = irb->mt->surf.row_pitch;
+ image->pitch = irb->mt->surf.row_pitch_B;
image->dri_format = driGLFormatToImageFormat(image->format);
image->has_depthstencil = irb->mt->stencil_mt? true : false;
}
} else {
assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
- aux_surf.size = 0;
+ aux_surf.size_B = 0;
}
/* We request that the bufmgr zero the buffer for us for two reasons:
* in the pass-through state which is what we want.
*/
image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
- surf.size + aux_surf.size,
+ surf.size_B + aux_surf.size_B,
BRW_MEMZONE_OTHER,
isl_tiling_to_i915_tiling(mod_info->tiling),
- surf.row_pitch, BO_ALLOC_ZEROED);
+ surf.row_pitch_B, BO_ALLOC_ZEROED);
if (image->bo == NULL) {
free(image);
return NULL;
}
image->width = width;
image->height = height;
- image->pitch = surf.row_pitch;
+ image->pitch = surf.row_pitch_B;
image->modifier = modifier;
- if (aux_surf.size) {
- image->aux_offset = surf.size;
- image->aux_pitch = aux_surf.row_pitch;
- image->aux_size = aux_surf.size;
+ if (aux_surf.size_B) {
+ image->aux_offset = surf.size_B;
+ image->aux_pitch = aux_surf.row_pitch_B;
+ image->aux_size = aux_surf.size_B;
}
return image;
image->tile_y = orig_image->tile_y;
image->has_depthstencil = orig_image->has_depthstencil;
image->data = loaderPrivate;
- image->dma_buf_imported = orig_image->dma_buf_imported;
image->aux_offset = orig_image->aux_offset;
image->aux_pitch = orig_image->aux_pitch;
.levels = 1,
.array_len = 1,
.samples = 1,
- .row_pitch = strides[index],
+ .row_pitch_B = strides[index],
.usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_TEXTURE_BIT |
ISL_SURF_USAGE_STORAGE_BIT,
return NULL;
}
- const int end = offsets[index] + surf.size;
+ const int end = offsets[index] + surf.size_B;
if (size < end)
size = end;
}
return NULL;
}
- image->aux_size = aux_surf.size;
+ image->aux_size = aux_surf.size_B;
- const int end = image->aux_offset + aux_surf.size;
+ const int end = image->aux_offset + aux_surf.size_B;
if (size < end)
size = end;
} else {
return NULL;
}
- image->dma_buf_imported = true;
image->yuv_color_space = yuv_color_space;
image->sample_range = sample_range;
image->horizontal_siting = horizontal_siting;
intel_image_format_is_supported(const struct gen_device_info *devinfo,
const struct intel_image_format *fmt)
{
- if (fmt->fourcc == __DRI_IMAGE_FOURCC_SARGB8888 ||
- fmt->fourcc == __DRI_IMAGE_FOURCC_SABGR8888)
- return false;
+ /* Currently, all formats with an intel_image_format are available on all
+ * platforms so there's really nothing to check there.
+ */
#ifndef NDEBUG
if (fmt->nplanes == 1) {
int num_formats = 0, i;
for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
+ /* These two formats are valid DRI formats but do not exist in
+ * drm_fourcc.h in the Linux kernel. We don't want to accidentally
+ * advertise them through the EGL layer.
+ */
+ if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 ||
+ intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888)
+ continue;
+
if (!intel_image_format_is_supported(&screen->devinfo,
&intel_image_formats[i]))
continue;
for (i = 0; i < num_mods && i < max; i++) {
if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
- f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) {
+ f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV ||
+ f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) {
external_only[i] = GL_TRUE;
}
else {
.set_cache_funcs = brw_set_cache_funcs
};
+static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension = {
+ .base = { __DRI_MUTABLE_RENDER_BUFFER_DRIVER, 1 },
+};
+
static const __DRIextension *screenExtensions[] = {
&intelTexBufferExtension.base,
&intelFenceExtension.base,
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
+ &intelMutableRenderBufferExtension.base,
&dri2ConfigQueryExtension.base,
&dri2NoErrorExtension.base,
&intelBlobExtension.base,
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
+ &intelMutableRenderBufferExtension.base,
&dri2ConfigQueryExtension.base,
&dri2Robustness.base,
&dri2NoErrorExtension.base,
static bool
intel_detect_swizzling(struct intel_screen *screen)
{
+ /* Broadwell PRM says:
+ *
+ * "Before Gen8, there was a historical configuration control field to
+ * swizzle address bit[6] for in X/Y tiling modes. This was set in three
+ * different places: TILECTL[1:0], ARB_MODE[5:4], and
+ * DISP_ARB_CTL[14:13].
+ *
+ * For Gen8 and subsequent generations, the swizzle fields are all
+ * reserved, and the CPU's memory controller performs all address
+ * swizzling modifications."
+ */
+ if (screen->devinfo.gen >= 8)
+ return false;
+
uint32_t tiling = I915_TILING_X;
uint32_t swizzle_mode = 0;
struct brw_bo *buffer =
MESA_FORMAT_R8G8B8A8_SRGB,
};
- /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
+ /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
static const GLenum back_buffer_modes[] = {
__DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE
};
/* Shall we expose 10 bpc formats? */
bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache,
"allow_rgb10_configs");
+ /* Shall we expose 565 formats? */
+ bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache,
+ "allow_rgb565_configs");
- /* Generate singlesample configs without accumulation buffer. */
+ /* Generate singlesample configs, each without accumulation buffer
+ * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
+ */
for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
int num_depth_stencil_bits = 2;
formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
continue;
+ if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM)
+ continue;
+
/* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
* buffer that has a different number of bits per pixel than the color
* buffer, gen >= 6 supports this.
num_depth_stencil_bits,
back_buffer_modes, 2,
singlesample_samples, 1,
- false, false, false);
+ false, false,
+ /*mutable_render_buffer*/ true);
configs = driConcatConfigs(configs, new_configs);
}
formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
continue;
+ if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM)
+ continue;
+
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
depth_bits[0] = 16;
stencil_bits[0] = 0;
formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
continue;
+ if (!allow_rgb565_configs && formats[i] == MESA_FORMAT_B5G6R5_UNORM)
+ continue;
+
__DRIconfig **new_configs;
const int num_depth_stencil_bits = 2;
int num_msaa_modes = 0;
* Return the revision (generally the revid field of the PCI header) of the
* graphics device.
*/
-int
+static int
intel_device_get_revision(int fd)
{
struct drm_i915_getparam gp;
va_start(args, fmt);
GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_OTHER,
- MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
+ _mesa_gl_vdebugf(&brw->ctx, &msg_id,
+ MESA_DEBUG_SOURCE_SHADER_COMPILER,
+ MESA_DEBUG_TYPE_OTHER,
+ MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
va_end(args);
}
if (brw->perf_debug) {
GLuint msg_id = 0;
- _mesa_gl_vdebug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_PERFORMANCE,
- MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
+ _mesa_gl_vdebugf(&brw->ctx, &msg_id,
+ MESA_DEBUG_SOURCE_SHADER_COMPILER,
+ MESA_DEBUG_TYPE_PERFORMANCE,
+ MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
}
va_end(args);
}
memset(&options, 0, sizeof(options));
driParseOptionInfo(&options, brw_config_options.xml);
- driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum, "i965");
+ driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum,
+ "i965", NULL);
driDestroyOptionCache(&options);
screen->driScrnPriv = dri_screen;
if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
return NULL;
+ screen->devinfo.revision = intel_device_get_revision(dri_screen->fd);
+
if (!intel_init_bufmgr(screen))
return NULL;
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