#include "main/fbobject.h"
#include "main/version.h"
#include "swrast/s_renderbuffer.h"
-#include "glsl/ralloc.h"
+#include "util/ralloc.h"
+#include "brw_shader.h"
+#include "glsl/nir/nir.h"
#include "utils.h"
#include "xmlpool.h"
DRI_CONF_OPT_BEGIN_B(hiz, "true")
DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+")
DRI_CONF_OPT_END
-
- DRI_CONF_OPT_BEGIN_B(disable_derivative_optimization, "false")
- DRI_CONF_DESC(en, "Derivatives with finer granularity by default")
- DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
+ DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
DRI_CONF_DESC(en, "Perform code generation at shader link time.")
#include "intel_batchbuffer.h"
#include "intel_buffers.h"
#include "intel_bufmgr.h"
-#include "intel_chipset.h"
#include "intel_fbo.h"
#include "intel_mipmap_tree.h"
#include "intel_screen.h"
#include "intel_tex.h"
-#include "intel_regions.h"
+#include "intel_image.h"
#include "brw_context.h"
{
struct gl_framebuffer *fb = ctx->DrawBuffer;
- for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
+ for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
struct intel_renderbuffer *irb =
intel_renderbuffer(fb->_ColorDrawBuffers[i]);
continue;
}
- assert(irb->mt->region->pitch % irb->mt->region->cpp == 0);
- drm_intel_gem_bo_aub_dump_bmp(irb->mt->region->bo,
+ drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo,
irb->draw_x,
irb->draw_y,
irb->Base.Base.Width,
irb->Base.Base.Height,
format,
- irb->mt->region->pitch,
+ irb->mt->pitch,
0);
}
}
if (flags & __DRI2_FLUSH_DRAWABLE)
intel_resolve_for_dri2_flush(brw, dPriv);
- if (reason == __DRI2_THROTTLE_SWAPBUFFER ||
- reason == __DRI2_THROTTLE_FLUSHFRONT) {
- brw->need_throttle = true;
- }
+ if (reason == __DRI2_THROTTLE_SWAPBUFFER)
+ brw->need_swap_throttle = true;
+ if (reason == __DRI2_THROTTLE_FLUSHFRONT)
+ brw->need_flush_throttle = true;
intel_batchbuffer_flush(brw);
{ __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
+ { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
+
{ __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
{ __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } },
+ { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } },
+
{ __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
+ { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
+
+ { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
+
{ __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
return f;
}
+static boolean intel_lookup_fourcc(int dri_format, int *fourcc)
+{
+ for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
+ if (intel_image_formats[i].planes[0].dri_format == dri_format) {
+ *fourcc = intel_image_formats[i].fourcc;
+ return true;
+ }
+ }
+ return false;
+}
+
static __DRIimage *
intel_allocate_image(int dri_format, void *loaderPrivate)
{
image->width = minify(mt->physical_width0, level - mt->first_level);
image->height = minify(mt->physical_height0, level - mt->first_level);
- image->pitch = mt->region->pitch;
+ image->pitch = mt->pitch;
image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
&image->tile_x,
&image->tile_y);
drm_intel_bo_unreference(image->bo);
- image->bo = mt->region->bo;
- drm_intel_bo_reference(mt->region->bo);
+ image->bo = mt->bo;
+ drm_intel_bo_reference(mt->bo);
}
static __DRIimage *
image->offset = 0;
image->data = loaderPrivate;
drm_intel_bo_unreference(image->bo);
- image->bo = irb->mt->region->bo;
- drm_intel_bo_reference(irb->mt->region->bo);
- image->width = irb->mt->region->width;
- image->height = irb->mt->region->height;
- image->pitch = irb->mt->region->pitch;
+ image->bo = irb->mt->bo;
+ drm_intel_bo_reference(irb->mt->bo);
+ image->width = rb->Width;
+ image->height = rb->Height;
+ image->pitch = irb->mt->pitch;
image->dri_format = driGLFormatToImageFormat(image->format);
image->has_depthstencil = irb->mt->stencil_mt? true : false;
if (drm_intel_bo_gem_export_to_prime(image->bo, value) == 0)
return true;
return false;
+ case __DRI_IMAGE_ATTRIB_FOURCC:
+ if (intel_lookup_fourcc(image->dri_format, value))
+ return true;
+ return false;
+ case __DRI_IMAGE_ATTRIB_NUM_PLANES:
+ *value = 1;
+ return true;
+
default:
return false;
}
if (f->nplanes == 1) {
image->offset = image->offsets[0];
- intel_image_warn_if_unaligned(image, __FUNCTION__);
+ intel_image_warn_if_unaligned(image, __func__);
}
return image;
image->pitch = stride;
image->offset = offset;
- intel_image_warn_if_unaligned(image, __FUNCTION__);
+ intel_image_warn_if_unaligned(image, __func__);
return image;
}
static const __DRIimageExtension intelImageExtension = {
- .base = { __DRI_IMAGE, 8 },
+ .base = { __DRI_IMAGE, 11 },
.createImageFromName = intel_create_image_from_name,
.createImageFromRenderbuffer = intel_create_image_from_renderbuffer,
.fromPlanar = intel_from_planar,
.createImageFromTexture = intel_create_image_from_texture,
.createImageFromFds = intel_create_image_from_fds,
- .createImageFromDmaBufs = intel_create_image_from_dma_bufs
+ .createImageFromDmaBufs = intel_create_image_from_dma_bufs,
+ .blitImage = NULL,
+ .getCapabilities = NULL
};
static int
case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE:
value[0] = 1;
return 0;
- case __DRI2_RENDERER_PREFERRED_PROFILE:
- value[0] = (psp->max_gl_core_version != 0)
- ? (1U << __DRI_API_OPENGL_CORE) : (1U << __DRI_API_OPENGL);
- return 0;
default:
return driQueryRendererIntegerCommon(psp, param, value);
}
static const __DRIextension *intelScreenExtensions[] = {
&intelTexBufferExtension.base,
+ &intelFenceExtension.base,
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
static const __DRIextension *intelRobustScreenExtensions[] = {
&intelTexBufferExtension.base,
+ &intelFenceExtension.base,
&intelFlushExtension.base,
&intelImageExtension.base,
&intelRendererQueryExtension.base,
return true;
}
+static int
+intel_detect_timestamp(struct intel_screen *screen)
+{
+ uint64_t dummy = 0, last = 0;
+ int upper, lower, loops;
+
+ /* On 64bit systems, some old kernels trigger a hw bug resulting in the
+ * TIMESTAMP register being shifted and the low 32bits always zero.
+ *
+ * More recent kernels offer an interface to read the full 36bits
+ * everywhere.
+ */
+ if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0)
+ return 3;
+
+ /* Determine if we have a 32bit or 64bit kernel by inspecting the
+ * upper 32bits for a rapidly changing timestamp.
+ */
+ if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &last))
+ return 0;
+
+ upper = lower = 0;
+ for (loops = 0; loops < 10; loops++) {
+ /* The TIMESTAMP should change every 80ns, so several round trips
+ * through the kernel should be enough to advance it.
+ */
+ if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy))
+ return 0;
+
+ upper += (dummy >> 32) != (last >> 32);
+ if (upper > 1) /* beware 32bit counter overflow */
+ return 2; /* upper dword holds the low 32bits of the timestamp */
+
+ lower += (dummy & 0xffffffff) != (last & 0xffffffff);
+ if (lower > 1)
+ return 1; /* timestamp is unshifted */
+
+ last = dummy;
+ }
+
+ /* No advancement? No timestamp! */
+ return 0;
+}
+
/**
* Return array of MSAA modes supported by the hardware. The array is
* zero-terminated and sorted in decreasing order.
{
static const mesa_format formats[] = {
MESA_FORMAT_B5G6R5_UNORM,
- MESA_FORMAT_B8G8R8A8_UNORM
+ MESA_FORMAT_B8G8R8A8_UNORM,
+ MESA_FORMAT_B8G8R8X8_UNORM
};
/* GLX_SWAP_COPY_OML is not supported due to page flipping. */
__DRIconfig **configs = NULL;
/* Generate singlesample configs without accumulation buffer. */
- for (int i = 0; i < ARRAY_SIZE(formats); i++) {
+ for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) {
__DRIconfig **new_configs;
int num_depth_stencil_bits = 2;
/* Generate the minimum possible set of configs that include an
* accumulation buffer.
*/
- for (int i = 0; i < ARRAY_SIZE(formats); i++) {
+ for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) {
__DRIconfig **new_configs;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
* supported. Singlebuffer configs are not supported because no one wants
* them.
*/
- for (int i = 0; i < ARRAY_SIZE(formats); i++) {
+ for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) {
if (devinfo->gen < 6)
break;
__DRIscreen *psp = screen->driScrnPriv;
switch (screen->devinfo->gen) {
+ case 9:
case 8:
case 7:
- psp->max_gl_core_version = 33;
- psp->max_gl_compat_version = 30;
- psp->max_gl_es1_version = 11;
- psp->max_gl_es2_version = 30;
- break;
case 6:
- psp->max_gl_core_version = 31;
+ psp->max_gl_core_version = 33;
psp->max_gl_compat_version = 30;
psp->max_gl_es1_version = 11;
psp->max_gl_es2_version = 30;
psp->max_gl_es2_version = 20;
break;
default:
- assert(!"unrecognized intel_screen::gen");
- break;
+ unreachable("unrecognized intel_screen::gen");
}
}
+static int
+brw_get_revision(int fd)
+{
+ struct drm_i915_getparam gp;
+ int revision;
+ int ret;
+
+ memset(&gp, 0, sizeof(gp));
+ gp.param = I915_PARAM_REVISION;
+ gp.value = &revision;
+
+ ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
+ if (ret)
+ revision = -1;
+
+ return revision;
+}
+
+/* Drop when RS headers get pulled to libdrm */
+#ifndef I915_PARAM_HAS_RESOURCE_STREAMER
+#define I915_PARAM_HAS_RESOURCE_STREAMER 36
+#endif
+
/**
* This is the driver specific part of the createNewScreen entry point.
* Called when using DRI2.
return false;
intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr);
- intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID);
+ intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID,
+ brw_get_revision(psp->fd));
if (!intelScreen->devinfo)
return false;
+ brw_process_intel_debug_variable(intelScreen);
+
intelScreen->hw_must_use_separate_stencil = intelScreen->devinfo->gen >= 7;
intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen);
+ intelScreen->hw_has_timestamp = intel_detect_timestamp(intelScreen);
const char *force_msaa = getenv("INTEL_FORCE_MSAA");
if (force_msaa) {
(ret != -1 || errno != EINVAL);
}
+ struct drm_i915_getparam getparam;
+ getparam.param = I915_PARAM_CMD_PARSER_VERSION;
+ getparam.value = &intelScreen->cmd_parser_version;
+ const int ret = drmIoctl(psp->fd, DRM_IOCTL_I915_GETPARAM, &getparam);
+ if (ret == -1)
+ intelScreen->cmd_parser_version = 0;
+
psp->extensions = !intelScreen->has_context_reset_notification
? intelScreenExtensions : intelRobustScreenExtensions;
- brw_fs_alloc_reg_sets(intelScreen);
- brw_vec4_alloc_reg_set(intelScreen);
+ intelScreen->compiler = brw_compiler_create(intelScreen,
+ intelScreen->devinfo);
+
+ if (intelScreen->devinfo->has_resource_streamer) {
+ int val = -1;
+ getparam.param = I915_PARAM_HAS_RESOURCE_STREAMER;
+ getparam.value = &val;
+
+ drmIoctl(psp->fd, DRM_IOCTL_I915_GETPARAM, &getparam);
+ intelScreen->has_resource_streamer = val > 0;
+ }
return (const __DRIconfig**) intel_screen_make_configs(psp);
}
+struct intel_screen *
+intel_screen_create(int fd)
+{
+ __DRIscreen *psp;
+ __DRIconfig **configs;
+ int i;
+
+ psp = malloc(sizeof(*psp));
+ if (psp == NULL)
+ return NULL;
+
+ psp->image.loader = (void *) 1; /* Don't complain about this being NULL */
+ psp->fd = fd;
+ psp->dri2.useInvalidate = (void *) 1;
+
+ configs = (__DRIconfig **) intelInitScreen2(psp);
+ for (i = 0; configs[i]; i++)
+ free(configs[i]);
+ free(configs);
+
+ return psp->driverPrivate;
+}
+
+void
+intel_screen_destroy(struct intel_screen *screen)
+{
+ __DRIscreen *psp;
+
+ psp = screen->driScrnPriv;
+ intelDestroyScreen(screen->driScrnPriv);
+ free(psp);
+}
+
+
+struct brw_context *
+intel_context_create(struct intel_screen *screen)
+{
+ __DRIcontext *driContextPriv;
+ struct brw_context *brw;
+ unsigned error;
+
+ driContextPriv = malloc(sizeof(*driContextPriv));
+ if (driContextPriv == NULL)
+ return NULL;
+
+ driContextPriv->driScreenPriv = screen->driScrnPriv;
+
+ brwCreateContext(API_OPENGL_CORE,
+ NULL, /* visual */
+ driContextPriv,
+ 3, 0,
+ 0, /* flags */
+ false, /* notify_reset */
+ &error,
+ NULL);
+
+ brw = driContextPriv->driverPrivate;
+ brw->ctx.FirstTimeCurrent = false;
+
+ return driContextPriv->driverPrivate;
+}
+
+void
+intel_context_destroy(struct brw_context *brw)
+{
+ __DRIcontext *driContextPriv;
+
+ driContextPriv = brw->driContext;
+ intelDestroyContext(driContextPriv);
+ free(driContextPriv);
+}
+
struct intel_buffer {
__DRIbuffer base;
- struct intel_region *region;
+ drm_intel_bo *bo;
};
static __DRIbuffer *
return NULL;
/* The front and back buffers are color buffers, which are X tiled. */
- intelBuffer->region = intel_region_alloc(intelScreen,
- I915_TILING_X,
- format / 8,
- width,
- height,
- true);
-
- if (intelBuffer->region == NULL) {
+ uint32_t tiling = I915_TILING_X;
+ unsigned long pitch;
+ int cpp = format / 8;
+ intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr,
+ "intelAllocateBuffer",
+ width,
+ height,
+ cpp,
+ &tiling, &pitch,
+ BO_ALLOC_FOR_RENDER);
+
+ if (intelBuffer->bo == NULL) {
free(intelBuffer);
return NULL;
}
- drm_intel_bo_flink(intelBuffer->region->bo, &intelBuffer->base.name);
+ drm_intel_bo_flink(intelBuffer->bo, &intelBuffer->base.name);
intelBuffer->base.attachment = attachment;
- intelBuffer->base.cpp = intelBuffer->region->cpp;
- intelBuffer->base.pitch = intelBuffer->region->pitch;
+ intelBuffer->base.cpp = cpp;
+ intelBuffer->base.pitch = pitch;
return &intelBuffer->base;
}
{
struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer;
- intel_region_release(&intelBuffer->region);
+ drm_intel_bo_unreference(intelBuffer->bo);
free(intelBuffer);
}