* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <drm_fourcc.h>
#include <errno.h>
#include <time.h>
#include <unistd.h>
#define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
#endif
+#ifndef DRM_FORMAT_MOD_LINEAR
+#define DRM_FORMAT_MOD_LINEAR 0
+#endif
+
static const __DRIconfigOptionsExtension brw_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
.xml =
DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
+ DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
DRI_CONF_DESC(en, "Perform code generation at shader link time.")
free(image);
}
+enum modifier_priority {
+ MODIFIER_PRIORITY_INVALID = 0,
+ MODIFIER_PRIORITY_LINEAR,
+ MODIFIER_PRIORITY_X,
+ MODIFIER_PRIORITY_Y,
+};
+
+const uint64_t priority_to_modifier[] = {
+ [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
+ [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
+ [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
+ [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
+};
+
static uint64_t
select_best_modifier(struct gen_device_info *devinfo,
const uint64_t *modifiers,
const unsigned count)
{
- /* Modifiers are not supported by this DRI driver */
- return DRM_FORMAT_MOD_INVALID;
+ enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
+
+ for (int i = 0; i < count; i++) {
+ switch (modifiers[i]) {
+ case I915_FORMAT_MOD_Y_TILED:
+ prio = MAX2(prio, MODIFIER_PRIORITY_Y);
+ break;
+ case I915_FORMAT_MOD_X_TILED:
+ prio = MAX2(prio, MODIFIER_PRIORITY_X);
+ break;
+ case DRM_FORMAT_MOD_LINEAR:
+ prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
+ break;
+ case DRM_FORMAT_MOD_INVALID:
+ default:
+ break;
+ }
+ }
+
+ return priority_to_modifier[prio];
}
static __DRIimage *
{
__DRIimage *image;
struct intel_screen *screen = dri_screen->driverPrivate;
- uint32_t tiling;
+ /* Historically, X-tiled was the default, and so lack of modifier means
+ * X-tiled.
+ */
+ uint32_t tiling = I915_TILING_X;
int cpp;
unsigned long pitch;
assert(!(use && count));
uint64_t modifier = select_best_modifier(&screen->devinfo, modifiers, count);
- assert(modifier == DRM_FORMAT_MOD_INVALID);
-
- if (modifier == DRM_FORMAT_MOD_INVALID && modifiers)
- return NULL;
+ switch (modifier) {
+ case I915_FORMAT_MOD_X_TILED:
+ assert(tiling == I915_TILING_X);
+ break;
+ case DRM_FORMAT_MOD_LINEAR:
+ tiling = I915_TILING_NONE;
+ break;
+ case I915_FORMAT_MOD_Y_TILED:
+ tiling = I915_TILING_Y;
+ break;
+ case DRM_FORMAT_MOD_INVALID:
+ if (modifiers)
+ return NULL;
+ default:
+ break;
+ }
- /* Historically, X-tiled was the default, and so lack of modifier means
- * X-tiled.
- */
- tiling = I915_TILING_X;
if (use & __DRI_IMAGE_USE_CURSOR) {
if (width != 64 || height != 64)
return NULL;
image->width = width;
image->height = height;
image->pitch = pitch;
+ image->modifier = modifier;
return image;
}
const unsigned count,
void *loaderPrivate)
{
- return intel_create_image_common(dri_screen, width, height, format, 0, NULL,
- 0, loaderPrivate);
+ return intel_create_image_common(dri_screen, width, height, format, 0,
+ modifiers, count, loaderPrivate);
}
static GLboolean
}
static const __DRIimageExtension intelImageExtension = {
- .base = { __DRI_IMAGE, 13 },
+ .base = { __DRI_IMAGE, 14 },
.createImageFromName = intel_create_image_from_name,
.createImageFromRenderbuffer = intel_create_image_from_renderbuffer,
{
struct intel_screen *screen = sPriv->driverPrivate;
- dri_bufmgr_destroy(screen->bufmgr);
+ drm_intel_bufmgr_destroy(screen->bufmgr);
driDestroyOptionInfo(&screen->optionCache);
ralloc_free(screen);
/* setup the hardware-based renderbuffers */
rb = intel_create_renderbuffer(rgbFormat, num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
if (mesaVis->doubleBufferMode) {
rb = intel_create_renderbuffer(rgbFormat, num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
}
/*
if (screen->devinfo.has_hiz_and_separate_stencil) {
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
rb = intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_STENCIL,
+ &rb->Base.Base);
} else {
/*
* Use combined depth/stencil. Note that the renderbuffer is
*/
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
}
}
assert(mesaVis->stencilBits == 0);
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
}
else {
assert(mesaVis->depthBits == 0);
screen->no_hw = getenv("INTEL_NO_HW") != NULL;
- screen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
+ screen->bufmgr = drm_intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
drm_intel_bufmgr_gem_enable_fenced_relocs(screen->bufmgr);
- if (!intel_get_boolean(screen, I915_PARAM_HAS_RELAXED_DELTA)) {
- fprintf(stderr, "[%s: %u] Kernel 2.6.39 required.\n", __func__, __LINE__);
+ if (!intel_get_boolean(screen, I915_PARAM_HAS_WAIT_TIMEOUT)) {
+ fprintf(stderr, "[%s: %u] Kernel 3.6 required.\n", __func__, __LINE__);
return false;
}
brw_process_intel_debug_variable();
if (INTEL_DEBUG & DEBUG_BUFMGR)
- dri_bufmgr_set_debug(screen->bufmgr, true);
+ drm_intel_bufmgr_set_debug(screen->bufmgr, true);
if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
fprintf(stderr,
if (intelBuffer == NULL)
return NULL;
- /* The front and back buffers are color buffers, which are X tiled. */
+ /* The front and back buffers are color buffers, which are X tiled. GEN9+
+ * supports Y tiled and compressed buffers, but there is no way to plumb that
+ * through to here. */
uint32_t tiling = I915_TILING_X;
unsigned long pitch;
int cpp = format / 8;
projects / mesa.git / blobdiff