* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <drm_fourcc.h>
#include <errno.h>
#include <time.h>
#include <unistd.h>
#include "main/version.h"
#include "swrast/s_renderbuffer.h"
#include "util/ralloc.h"
-#include "brw_shader.h"
+#include "brw_defines.h"
#include "compiler/nir/nir.h"
#include "utils.h"
#include "xmlpool.h"
+#ifndef DRM_FORMAT_MOD_INVALID
+#define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
+#endif
+
+#ifndef DRM_FORMAT_MOD_LINEAR
+#define DRM_FORMAT_MOD_LINEAR 0
+#endif
+
static const __DRIconfigOptionsExtension brw_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
.xml =
DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
DRI_CONF_DESC_END
DRI_CONF_OPT_END
-
- DRI_CONF_OPT_BEGIN_B(hiz, "true")
- DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+")
- DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
DRI_CONF_DISABLE_THROTTLING("false")
DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
+ DRI_CONF_FORCE_GLSL_VERSION(0)
DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
+ DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
+ DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
DRI_CONF_DESC(en, "Perform code generation at shader link time.")
return tp.tv_sec + tp.tv_nsec / 1000000000.0;
}
-void
-aub_dump_bmp(struct gl_context *ctx)
-{
- struct gl_framebuffer *fb = ctx->DrawBuffer;
-
- for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
- struct intel_renderbuffer *irb =
- intel_renderbuffer(fb->_ColorDrawBuffers[i]);
-
- if (irb && irb->mt) {
- enum aub_dump_bmp_format format;
-
- switch (irb->Base.Base.Format) {
- case MESA_FORMAT_B8G8R8A8_UNORM:
- case MESA_FORMAT_B8G8R8X8_UNORM:
- format = AUB_DUMP_BMP_FORMAT_ARGB_8888;
- break;
- default:
- continue;
- }
-
- drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo,
- irb->draw_x,
- irb->draw_y,
- irb->Base.Base.Width,
- irb->Base.Base.Height,
- format,
- irb->mt->pitch,
- 0);
- }
- }
-}
-
static const __DRItexBufferExtension intelTexBufferExtension = {
.base = { __DRI_TEX_BUFFER, 3 },
brw->need_flush_throttle = true;
intel_batchbuffer_flush(brw);
-
- if (INTEL_DEBUG & DEBUG_AUB) {
- aub_dump_bmp(ctx);
- }
}
/**
{ __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
+ { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } },
+
{ __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
+ { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } },
+
{ __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
}
static __DRIimage *
-intel_allocate_image(int dri_format, void *loaderPrivate)
+intel_allocate_image(struct intel_screen *screen, int dri_format,
+ void *loaderPrivate)
{
__DRIimage *image;
if (image == NULL)
return NULL;
+ image->screen = screen;
image->dri_format = dri_format;
image->offset = 0;
__DRIimage *image;
int cpp;
- image = intel_allocate_image(format, loaderPrivate);
+ image = intel_allocate_image(screen, format, loaderPrivate);
if (image == NULL)
return NULL;
free(image);
}
+enum modifier_priority {
+ MODIFIER_PRIORITY_INVALID = 0,
+ MODIFIER_PRIORITY_LINEAR,
+ MODIFIER_PRIORITY_X,
+ MODIFIER_PRIORITY_Y,
+};
+
+const uint64_t priority_to_modifier[] = {
+ [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
+ [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
+ [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
+ [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
+};
+
+static uint64_t
+select_best_modifier(struct gen_device_info *devinfo,
+ const uint64_t *modifiers,
+ const unsigned count)
+{
+ enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
+
+ for (int i = 0; i < count; i++) {
+ switch (modifiers[i]) {
+ case I915_FORMAT_MOD_Y_TILED:
+ prio = MAX2(prio, MODIFIER_PRIORITY_Y);
+ break;
+ case I915_FORMAT_MOD_X_TILED:
+ prio = MAX2(prio, MODIFIER_PRIORITY_X);
+ break;
+ case DRM_FORMAT_MOD_LINEAR:
+ prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
+ break;
+ case DRM_FORMAT_MOD_INVALID:
+ default:
+ break;
+ }
+ }
+
+ return priority_to_modifier[prio];
+}
+
static __DRIimage *
-intel_create_image(__DRIscreen *dri_screen,
- int width, int height, int format,
- unsigned int use,
- void *loaderPrivate)
+intel_create_image_common(__DRIscreen *dri_screen,
+ int width, int height, int format,
+ unsigned int use,
+ const uint64_t *modifiers,
+ unsigned count,
+ void *loaderPrivate)
{
__DRIimage *image;
struct intel_screen *screen = dri_screen->driverPrivate;
- uint32_t tiling;
+ /* Historically, X-tiled was the default, and so lack of modifier means
+ * X-tiled.
+ */
+ uint32_t tiling = I915_TILING_X;
int cpp;
unsigned long pitch;
- tiling = I915_TILING_X;
+ /* Callers of this may specify a modifier, or a dri usage, but not both. The
+ * newer modifier interface deprecates the older usage flags newer modifier
+ * interface deprecates the older usage flags.
+ */
+ assert(!(use && count));
+
+ uint64_t modifier = select_best_modifier(&screen->devinfo, modifiers, count);
+ switch (modifier) {
+ case I915_FORMAT_MOD_X_TILED:
+ assert(tiling == I915_TILING_X);
+ break;
+ case DRM_FORMAT_MOD_LINEAR:
+ tiling = I915_TILING_NONE;
+ break;
+ case I915_FORMAT_MOD_Y_TILED:
+ tiling = I915_TILING_Y;
+ break;
+ case DRM_FORMAT_MOD_INVALID:
+ if (modifiers)
+ return NULL;
+ default:
+ break;
+ }
+
if (use & __DRI_IMAGE_USE_CURSOR) {
if (width != 64 || height != 64)
return NULL;
if (use & __DRI_IMAGE_USE_LINEAR)
tiling = I915_TILING_NONE;
- image = intel_allocate_image(format, loaderPrivate);
+ image = intel_allocate_image(screen, format, loaderPrivate);
if (image == NULL)
return NULL;
image->width = width;
image->height = height;
image->pitch = pitch;
+ image->modifier = modifier;
return image;
}
+static __DRIimage *
+intel_create_image(__DRIscreen *dri_screen,
+ int width, int height, int format,
+ unsigned int use,
+ void *loaderPrivate)
+{
+ return intel_create_image_common(dri_screen, width, height, format, use, NULL, 0,
+ loaderPrivate);
+}
+
+static __DRIimage *
+intel_create_image_with_modifiers(__DRIscreen *dri_screen,
+ int width, int height, int format,
+ const uint64_t *modifiers,
+ const unsigned count,
+ void *loaderPrivate)
+{
+ return intel_create_image_common(dri_screen, width, height, format, 0,
+ modifiers, count, loaderPrivate);
+}
+
static GLboolean
intel_query_image(__DRIimage *image, int attrib, int *value)
{
case __DRI_IMAGE_ATTRIB_OFFSET:
*value = image->offset;
return true;
+ case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER:
+ *value = (image->modifier & 0xffffffff);
+ return true;
+ case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER:
+ *value = ((image->modifier >> 32) & 0xffffffff);
+ return true;
default:
return false;
return NULL;
if (f->nplanes == 1)
- image = intel_allocate_image(f->planes[0].dri_format, loaderPrivate);
+ image = intel_allocate_image(screen, f->planes[0].dri_format,
+ loaderPrivate);
else
- image = intel_allocate_image(__DRI_IMAGE_FORMAT_NONE, loaderPrivate);
+ image = intel_allocate_image(screen, __DRI_IMAGE_FORMAT_NONE,
+ loaderPrivate);
if (image == NULL)
return NULL;
offset = parent->offsets[index];
stride = parent->strides[index];
- image = intel_allocate_image(dri_format, loaderPrivate);
+ image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
if (image == NULL)
return NULL;
}
static const __DRIimageExtension intelImageExtension = {
- .base = { __DRI_IMAGE, 13 },
+ .base = { __DRI_IMAGE, 14 },
.createImageFromName = intel_create_image_from_name,
.createImageFromRenderbuffer = intel_create_image_from_renderbuffer,
.getCapabilities = NULL,
.mapImage = NULL,
.unmapImage = NULL,
+ .createImageWithModifiers = intel_create_image_with_modifiers,
};
static int
{
struct intel_screen *screen = sPriv->driverPrivate;
- dri_bufmgr_destroy(screen->bufmgr);
+ drm_intel_bufmgr_destroy(screen->bufmgr);
driDestroyOptionInfo(&screen->optionCache);
ralloc_free(screen);
/* setup the hardware-based renderbuffers */
rb = intel_create_renderbuffer(rgbFormat, num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
if (mesaVis->doubleBufferMode) {
rb = intel_create_renderbuffer(rgbFormat, num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
}
/*
if (screen->devinfo.has_hiz_and_separate_stencil) {
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
rb = intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_STENCIL,
+ &rb->Base.Base);
} else {
/*
* Use combined depth/stencil. Note that the renderbuffer is
*/
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
}
}
assert(mesaVis->stencilBits == 0);
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
}
else {
assert(mesaVis->depthBits == 0);
screen->no_hw = getenv("INTEL_NO_HW") != NULL;
- screen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
+ screen->bufmgr = drm_intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
drm_intel_bufmgr_gem_enable_fenced_relocs(screen->bufmgr);
- if (!intel_get_boolean(screen, I915_PARAM_HAS_RELAXED_DELTA)) {
- fprintf(stderr, "[%s: %u] Kernel 2.6.39 required.\n", __func__, __LINE__);
+ if (!intel_get_boolean(screen, I915_PARAM_HAS_WAIT_TIMEOUT)) {
+ fprintf(stderr, "[%s: %u] Kernel 3.6 required.\n", __func__, __LINE__);
return false;
}
static bool
intel_detect_pipelined_so(struct intel_screen *screen)
{
+ const struct gen_device_info *devinfo = &screen->devinfo;
+
/* Supposedly, Broadwell just works. */
- if (screen->devinfo.gen >= 8)
+ if (devinfo->gen >= 8)
return true;
- if (screen->devinfo.gen <= 6)
+ if (devinfo->gen <= 6)
return false;
+ /* See the big explanation about command parser versions below */
+ if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2))
+ return true;
+
/* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
* statistics registers), and we already reset it to zero before using it.
*/
dri_screen->max_gl_es2_version = has_astc ? 32 : 31;
break;
case 7:
- dri_screen->max_gl_core_version = screen->devinfo.is_haswell &&
- can_do_pipelined_register_writes(screen) ? 45 : 33;
+ dri_screen->max_gl_core_version = 33;
+ if (screen->devinfo.is_haswell &&
+ can_do_pipelined_register_writes(screen)) {
+ dri_screen->max_gl_core_version = 42;
+ if (can_do_compute_dispatch(screen))
+ dri_screen->max_gl_core_version = 43;
+ if (can_do_mi_math_and_lrr(screen))
+ dri_screen->max_gl_core_version = 45;
+ }
dri_screen->max_gl_compat_version = 30;
dri_screen->max_gl_es1_version = 11;
dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30;
return revision;
}
-/* Drop when RS headers get pulled to libdrm */
-#ifndef I915_PARAM_HAS_RESOURCE_STREAMER
-#define I915_PARAM_HAS_RESOURCE_STREAMER 36
-#endif
-
static void
shader_debug_log_mesa(void *data, const char *fmt, ...)
{
fprintf(stderr,
"\nERROR! DRI2 loader with getBuffersWithFormat() "
"support required\n");
- return false;
+ return NULL;
}
/* Allocate the private area */
screen = rzalloc(NULL, struct intel_screen);
if (!screen) {
fprintf(stderr, "\nERROR! Allocating private area failed\n");
- return false;
+ return NULL;
}
/* parse information in __driConfigOptions */
driParseOptionInfo(&screen->optionCache, brw_config_options.xml);
dri_screen->driverPrivate = (void *) screen;
if (!intel_init_bufmgr(screen))
- return false;
+ return NULL;
screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr);
if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
- return false;
+ return NULL;
+
+ const struct gen_device_info *devinfo = &screen->devinfo;
brw_process_intel_debug_variable();
if (INTEL_DEBUG & DEBUG_BUFMGR)
- dri_bufmgr_set_debug(screen->bufmgr, true);
+ drm_intel_bufmgr_set_debug(screen->bufmgr, true);
- if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo.gen < 7) {
+ if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
fprintf(stderr,
"shader_time debugging requires gen7 (Ivybridge) or better.\n");
INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
}
- if (INTEL_DEBUG & DEBUG_AUB)
- drm_intel_bufmgr_gem_set_aub_dump(screen->bufmgr, true);
-
-#ifndef I915_PARAM_MMAP_GTT_VERSION
-#define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
-#endif
if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
/* Theorectically unlimited! At least for individual objects...
*
screen->hw_has_timestamp = intel_detect_timestamp(screen);
/* GENs prior to 8 do not support EU/Subslice info */
- if (screen->devinfo.gen >= 8) {
+ if (devinfo->gen >= 8) {
intel_detect_sseu(screen);
- } else if (screen->devinfo.gen == 7) {
- screen->subslice_total = 1 << (screen->devinfo.gt - 1);
+ } else if (devinfo->gen == 7) {
+ screen->subslice_total = 1 << (devinfo->gt - 1);
+ }
+
+ /* Gen7-7.5 kernel requirements / command parser saga:
+ *
+ * - pre-v3.16:
+ * Haswell and Baytrail cannot use any privileged batchbuffer features.
+ *
+ * Ivybridge has aliasing PPGTT on by default, which accidentally marks
+ * all batches secure, allowing them to use any feature with no checking.
+ * This is effectively equivalent to a command parser version of
+ * \infinity - everything is possible.
+ *
+ * The command parser does not exist, and querying the version will
+ * return -EINVAL.
+ *
+ * - v3.16:
+ * The kernel enables the command parser by default, for systems with
+ * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
+ * hardware checker is still enabled, so Haswell and Baytrail cannot
+ * do anything.
+ *
+ * Ivybridge goes from "everything is possible" to "only what the
+ * command parser allows" (if the user boots with i915.cmd_parser=0,
+ * then everything is possible again). We can only safely use features
+ * allowed by the supported command parser version.
+ *
+ * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
+ * implemented by the kernel, even if it's turned off. So, checking
+ * for version > 0 does not mean that you can write registers. We have
+ * to try it and see. The version does, however, indicate the age of
+ * the kernel.
+ *
+ * Instead of matching the hardware checker's behavior of converting
+ * privileged commands to MI_NOOP, it makes execbuf2 start returning
+ * -EINVAL, making it dangerous to try and use privileged features.
+ *
+ * Effective command parser versions:
+ * - Haswell: 0 (reporting 1, writes don't work)
+ * - Baytrail: 0 (reporting 1, writes don't work)
+ * - Ivybridge: 1 (enabled) or infinite (disabled)
+ *
+ * - v3.17:
+ * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
+ * effectively version 1 (enabled) or infinite (disabled).
+ *
+ * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
+ * Command parser v2 supports predicate writes.
+ *
+ * - Haswell: 0 (reporting 1, writes don't work)
+ * - Baytrail: 2 (enabled) or infinite (disabled)
+ * - Ivybridge: 2 (enabled) or infinite (disabled)
+ *
+ * So version >= 2 is enough to know that Ivybridge and Baytrail
+ * will work. Haswell still can't do anything.
+ *
+ * - v4.0: Version 3 happened. Largely not relevant.
+ *
+ * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
+ * L3 config registers are properly saved and restored as part
+ * of the hardware context. We can approximately detect this point
+ * in time by checking if I915_PARAM_REVISION is recognized - it
+ * landed in a later commit, but in the same release cycle.
+ *
+ * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
+ * Command parser finally gains secure batch promotion. On Haswell,
+ * the hardware checker gets disabled, which finally allows it to do
+ * privileged commands.
+ *
+ * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
+ * - Haswell: 3 (enabled) or 0 (disabled)
+ * - Baytrail: 3 (enabled) or infinite (disabled)
+ * - Ivybridge: 3 (enabled) or infinite (disabled)
+ *
+ * Unfortunately, detecting this point in time is tricky, because
+ * no version bump happened when this important change occurred.
+ * On Haswell, if we can write any register, then the kernel is at
+ * least this new, and we can start trusting the version number.
+ *
+ * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
+ * Command parser reaches version 4, allowing access to Haswell
+ * atomic scratch and chicken3 registers. If version >= 4, we know
+ * the kernel is new enough to support privileged features on all
+ * hardware. However, the user might have disabled it...and the
+ * kernel will still report version 4. So we still have to guess
+ * and check.
+ *
+ * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
+ * Command parser v5 whitelists indirect compute shader dispatch
+ * registers, needed for OpenGL 4.3 and later.
+ *
+ * - v4.8:
+ * Command parser v7 lets us use MI_MATH on Haswell.
+ *
+ * Additionally, the kernel begins reporting version 0 when
+ * the command parser is disabled, allowing us to skip the
+ * guess-and-check step on Haswell. Unfortunately, this also
+ * means that we can no longer use it as an indicator of the
+ * age of the kernel.
+ */
+ if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
+ &screen->cmd_parser_version) < 0) {
+ /* Command parser does not exist - getparam is unrecognized */
+ screen->cmd_parser_version = 0;
}
- if (intel_detect_pipelined_so(screen))
+ if (!intel_detect_pipelined_so(screen)) {
+ /* We can't do anything, so the effective version is 0. */
+ screen->cmd_parser_version = 0;
+ } else {
screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
+ }
const char *force_msaa = getenv("INTEL_FORCE_MSAA");
if (force_msaa) {
*
* Don't even try on pre-Gen6, since we don't attempt to use contexts there.
*/
- if (screen->devinfo.gen >= 6) {
+ if (devinfo->gen >= 6) {
struct drm_i915_reset_stats stats;
memset(&stats, 0, sizeof(stats));
(ret != -1 || errno != EINVAL);
}
- if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
- &screen->cmd_parser_version) < 0) {
- screen->cmd_parser_version = 0;
- }
-
- if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 2)
+ if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2)
screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
/* Haswell requires command parser version 4 in order to have L3
* atomic scratch1 and chicken3 bits
*/
- if (screen->devinfo.is_haswell && screen->cmd_parser_version >= 4) {
+ if (devinfo->is_haswell && screen->cmd_parser_version >= 4) {
screen->kernel_features |=
KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
}
* MI_MATH GPR registers, and version 7 in order to use
* MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
*/
- if (screen->devinfo.gen >= 8 ||
- (screen->devinfo.is_haswell && screen->cmd_parser_version >= 7)) {
+ if (devinfo->gen >= 8 ||
+ (devinfo->is_haswell && screen->cmd_parser_version >= 7)) {
screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
}
/* Gen7 needs at least command parser version 5 to support compute */
- if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 5)
+ if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
dri_screen->extensions = !screen->has_context_reset_notification
? screenExtensions : intelRobustScreenExtensions;
- screen->compiler = brw_compiler_create(screen,
- &screen->devinfo);
+ screen->compiler = brw_compiler_create(screen, devinfo);
screen->compiler->shader_debug_log = shader_debug_log_mesa;
screen->compiler->shader_perf_log = shader_perf_log_mesa;
screen->program_id = 1;
- if (screen->devinfo.has_resource_streamer) {
- screen->has_resource_streamer =
- intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER);
- }
+ screen->has_exec_fence =
+ intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
}
if (intelBuffer == NULL)
return NULL;
- /* The front and back buffers are color buffers, which are X tiled. */
+ /* The front and back buffers are color buffers, which are X tiled. GEN9+
+ * supports Y tiled and compressed buffers, but there is no way to plumb that
+ * through to here. */
uint32_t tiling = I915_TILING_X;
unsigned long pitch;
int cpp = format / 8;
projects / mesa.git / blobdiff