DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
+ DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
DRI_CONF_DESC(en, "Perform code generation at shader link time.")
{
struct intel_screen *screen = sPriv->driverPrivate;
- dri_bufmgr_destroy(screen->bufmgr);
+ drm_intel_bufmgr_destroy(screen->bufmgr);
driDestroyOptionInfo(&screen->optionCache);
ralloc_free(screen);
/* setup the hardware-based renderbuffers */
rb = intel_create_renderbuffer(rgbFormat, num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
if (mesaVis->doubleBufferMode) {
rb = intel_create_renderbuffer(rgbFormat, num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
}
/*
if (screen->devinfo.has_hiz_and_separate_stencil) {
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
rb = intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_STENCIL,
+ &rb->Base.Base);
} else {
/*
* Use combined depth/stencil. Note that the renderbuffer is
*/
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base);
}
}
assert(mesaVis->stencilBits == 0);
rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16,
num_samples);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
+ _mesa_add_renderbuffer_without_ref(fb, BUFFER_DEPTH, &rb->Base.Base);
}
else {
assert(mesaVis->depthBits == 0);
screen->no_hw = getenv("INTEL_NO_HW") != NULL;
- screen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
+ screen->bufmgr = drm_intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
drm_intel_bufmgr_gem_enable_fenced_relocs(screen->bufmgr);
- if (!intel_get_boolean(screen, I915_PARAM_HAS_RELAXED_DELTA)) {
- fprintf(stderr, "[%s: %u] Kernel 2.6.39 required.\n", __func__, __LINE__);
+ if (!intel_get_boolean(screen, I915_PARAM_HAS_WAIT_TIMEOUT)) {
+ fprintf(stderr, "[%s: %u] Kernel 3.6 required.\n", __func__, __LINE__);
return false;
}
brw_process_intel_debug_variable();
if (INTEL_DEBUG & DEBUG_BUFMGR)
- dri_bufmgr_set_debug(screen->bufmgr, true);
+ drm_intel_bufmgr_set_debug(screen->bufmgr, true);
if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
fprintf(stderr,