intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_syncobj.c

diff --git a/src/mesa/drivers/dri/i965/intel_syncobj.c b/src/mesa/drivers/dri/i965/intel_syncobj.c
index b6dfc5b059e55e1ffb6b077f4daf426b800bdeff..b7875eeba3dff1520aed66d225c1a4c264fcf149 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_syncobj.c
+++ b/src/mesa/drivers/dri/i965/intel_syncobj.c
@@ -69,16 +69,15 @@ intel_fence_sync(struct gl_context *ctx, struct gl_sync_object *s,
               GLenum condition, GLbitfield flags)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = intel_context(ctx);
    struct intel_sync_object *sync = (struct intel_sync_object *)s;
 
    assert(condition == GL_SYNC_GPU_COMMANDS_COMPLETE);
    intel_batchbuffer_emit_mi_flush(brw);
 
-   sync->bo = intel->batch.bo;
+   sync->bo = brw->batch.bo;
    drm_intel_bo_reference(sync->bo);
 
-   intel_flush(ctx);
+   intel_batchbuffer_flush(brw);
 }
 
 static void intel_client_wait_sync(struct gl_context *ctx, struct gl_sync_object *s,