i965/vec4: Simplify opt_reduce_swizzle() using the swizzle utils.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_syncobj.c

diff --git a/src/mesa/drivers/dri/i965/intel_syncobj.c b/src/mesa/drivers/dri/i965/intel_syncobj.c
index 9657d9af959b06e5334e2e2233654ce46d74fe48..e500fa04c5177adc876a6e31a321b54cf9ea0a1a 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_syncobj.c
+++ b/src/mesa/drivers/dri/i965/intel_syncobj.c
@@ -38,10 +38,9 @@
  * performance bottleneck, though.
  */
 
-#include "main/simple_list.h"
 #include "main/imports.h"
 
-#include "intel_context.h"
+#include "brw_context.h"
 #include "intel_batchbuffer.h"
 #include "intel_reg.h"
 
@@ -68,16 +67,16 @@ static void
 intel_fence_sync(struct gl_context *ctx, struct gl_sync_object *s,
               GLenum condition, GLbitfield flags)
 {
-   struct intel_context *intel = intel_context(ctx);
+   struct brw_context *brw = brw_context(ctx);
    struct intel_sync_object *sync = (struct intel_sync_object *)s;
 
    assert(condition == GL_SYNC_GPU_COMMANDS_COMPLETE);
-   intel_batchbuffer_emit_mi_flush(intel);
+   intel_batchbuffer_emit_mi_flush(brw);
 
-   sync->bo = intel->batch.bo;
+   sync->bo = brw->batch.bo;
    drm_intel_bo_reference(sync->bo);
 
-   intel_flush(ctx);
+   intel_batchbuffer_flush(brw);
 }
 
 static void intel_client_wait_sync(struct gl_context *ctx, struct gl_sync_object *s,
@@ -85,6 +84,14 @@ static void intel_client_wait_sync(struct gl_context *ctx, struct gl_sync_object
 {
    struct intel_sync_object *sync = (struct intel_sync_object *)s;
 
+   /* DRM_IOCTL_I915_GEM_WAIT uses a signed 64 bit timeout and returns
+    * immediately for timeouts <= 0.  The best we can do is to clamp the
+    * timeout to INT64_MAX.  This limits the maximum timeout from 584 years to
+    * 292 years - likely not a big deal.
+    */
+   if (timeout > INT64_MAX)
+      timeout = INT64_MAX;
+
    if (sync->bo && drm_intel_gem_bo_wait(sync->bo, timeout) == 0) {
       s->StatusFlag = 1;
       drm_intel_bo_unreference(sync->bo);