i965/nir: Sort uniforms direct-first and use two different uniform registers

[mesa.git] / src / mesa / drivers / dri / i965 / intel_tex.c

diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 184702fab9119ec05364295f1b905a578639f843..2d3009a30d12d89e8f7a32b03a533c71e07742ca 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -323,6 +323,11 @@ intel_set_texture_storage_for_buffer_object(struct gl_context *ctx,
          perf_debug("Bad PBO alignment; fallback to CPU mapping\n");
          return false;
       }
+
+      if (!brw->format_supported_as_render_target[image->TexFormat]) {
+         perf_debug("Non-renderable PBO format; fallback to CPU mapping\n");
+         return false;
+      }
    }
 
    assert(intel_texobj->mt == NULL);