i965/gen9: Optimize slice and subslice load balancing behavior.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_tex.h

diff --git a/src/mesa/drivers/dri/i965/intel_tex.h b/src/mesa/drivers/dri/i965/intel_tex.h
index 42565baebf672166f3bae7b20eb813284456ce17..4c48875f820b2d7cabe33720ef9e292f58377355 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex.h
+++ b/src/mesa/drivers/dri/i965/intel_tex.h
@@ -43,6 +43,8 @@ void intelSetTexBuffer(__DRIcontext *pDRICtx,
                       GLint target, __DRIdrawable *pDraw);
 void intelSetTexBuffer2(__DRIcontext *pDRICtx,
                        GLint target, GLint format, __DRIdrawable *pDraw);
+void intelReleaseTexBuffer(__DRIcontext *pDRICtx, GLint target,
+                           __DRIdrawable *dPriv);
 
 struct intel_mipmap_tree *
 intel_miptree_create_for_teximage(struct brw_context *brw,
@@ -50,6 +52,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
                                  struct intel_texture_image *intelImage,
                                   enum intel_miptree_create_flags flags);
 
-void intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit);
+void intel_finalize_mipmap_tree(struct brw_context *brw,
+                                struct gl_texture_object *tex_obj);
 
 #endif