intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / intel_tex_subimage.c

diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 1e4e98c2d7c5f7c2e4da1cd4e2cd6071cb57c2ad..05e684cf57b7717d3f57c8de94f36292397703e1 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -52,7 +52,6 @@ intel_blit_texsubimage(struct gl_context * ctx,
                       const struct gl_pixelstore_attrib *packing)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = intel_context(ctx);
    struct intel_texture_image *intelImage = intel_texture_image(texImage);
 
    /* Try to do a blit upload of the subimage if the texture is
@@ -71,7 +70,7 @@ intel_blit_texsubimage(struct gl_context * ctx,
    /* On gen6, it's probably not worth swapping to the blit ring to do
     * this because of all the overhead involved.
     */
-   if (intel->gen >= 6)
+   if (brw->gen >= 6)
       return false;
 
    if (!drm_intel_bo_busy(intelImage->mt->region->bo))
@@ -170,7 +169,6 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
                                bool for_glTexImage)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = intel_context(ctx);
    struct intel_texture_image *image = intel_texture_image(texImage);
 
    /* The miptree's buffer. */
@@ -182,7 +180,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
     * a 2D BGRA texture. It could be generalized to support more types by
     * varying the arithmetic loop below.
     */
-   if (!intel->has_llc ||
+   if (!brw->has_llc ||
        format != GL_BGRA ||
        type != GL_UNSIGNED_BYTE ||
        texImage->TexFormat != MESA_FORMAT_ARGB8888 ||