i965/nir/vec4: Implement single-element "mov" operations

[mesa.git] / src / mesa / drivers / dri / i965 / intel_tex_validate.c

diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 07f317441414ba89490d73ece35b8c09c714a958..6ebf381e6268c6876729653a63cc838b3badd474 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -47,8 +47,10 @@ intel_update_max_level(struct intel_texture_object *intelObj,
 {
    struct gl_texture_object *tObj = &intelObj->base;
 
-   if (sampler->MinFilter == GL_NEAREST ||
-       sampler->MinFilter == GL_LINEAR) {
+   if (!tObj->_MipmapComplete ||
+       (tObj->_RenderToTexture &&
+        (sampler->MinFilter == GL_NEAREST ||
+         sampler->MinFilter == GL_LINEAR))) {
       intelObj->_MaxLevel = tObj->BaseLevel;
    } else {
       intelObj->_MaxLevel = tObj->_MaxLevel;
@@ -98,20 +100,22 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
       return true;
    }
 
-   /* Immutable textures should not get this far -- they should have been
-    * created in a validated state, and nothing can invalidate them.
+   /* On recent generations, immutable textures should not get this far
+    * -- they should have been created in a validated state, and nothing
+    * can invalidate them.
+    *
+    * Unfortunately, this is not true on pre-Sandybridge hardware -- when
+    * rendering into an immutable-format depth texture we may have to rebase
+    * the rendered levels to meet alignment requirements.
+    *
+    * FINISHME: Avoid doing this.
     */
-   assert(!tObj->Immutable);
+   assert(!tObj->Immutable || brw->gen < 6);
 
    firstImage = intel_texture_image(tObj->Image[0][tObj->BaseLevel]);
 
    /* Check tree can hold all active levels.  Check tree matches
     * target, imageFormat, etc.
-    *
-    * For pre-gen4, we have to match first_level == tObj->BaseLevel,
-    * because we don't have the control that gen4 does to make min/mag
-    * determination happen at a nonzero (hardware) baselevel.  Because
-    * of that, we just always relayout on baselevel change.
     */
    if (intelObj->mt &&
        (!intel_miptree_match_image(intelObj->mt, &firstImage->base.Base) ||
@@ -132,6 +136,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
                  _mesa_get_format_name(firstImage->base.Base.TexFormat),
                  width, height, depth, validate_last_level + 1);
 
+      const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
+                                    MIPTREE_LAYOUT_ALLOC_ANY_TILED;
       intelObj->mt = intel_miptree_create(brw,
                                           intelObj->base.Target,
                                          firstImage->base.Base.TexFormat,
@@ -140,9 +146,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
                                           width,
                                           height,
                                           depth,
-                                         true,
                                           0 /* num_samples */,
-                                          INTEL_MIPTREE_TILING_ANY);
+                                          layout_flags);
       if (!intelObj->mt)
          return false;
    }