i965: Refactor SIMD16-to-2xSIMD8 checks.

[mesa.git] / src / mesa / drivers / dri / i965 / test_vec4_register_coalesce.cpp

diff --git a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
index 149174cebfcb45262078729379be1add62fd43d9..0c271629c0eefff9a251918a341fece7f5f8b11a 100644 (file)
--- a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
+++ b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
@@ -50,7 +50,7 @@ public:
                                   struct gl_shader_program *shader_prog)
       : vec4_visitor(brw, NULL, NULL, NULL, NULL, shader_prog,
                      MESA_SHADER_VERTEX, NULL,
-                     false, false /* no_spills */,
+                     false /* no_spills */,
                      ST_NONE, ST_NONE, ST_NONE)
    {
    }
@@ -119,6 +119,7 @@ _register_coalesce(vec4_visitor *v, const char *func)
       v->dump_instructions();
    }
 
+   v->calculate_cfg();
    v->opt_register_coalesce();
 
    if (print) {
@@ -241,8 +242,5 @@ TEST_F(register_coalesce_test, test_channel_mul_grf)
 
    register_coalesce(v);
 
-   /* This path isn't supported yet in the reswizzling code, so we're checking
-    * that we haven't done anything bad to scalar non-DP[234]s.
-    */
-   EXPECT_NE(mul->dst.reg, to.reg);
+   EXPECT_EQ(mul->dst.reg, to.reg);
 }