batch->buf = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
intel->maxBatchSize, 4096);
- batch->map = batch->buffer;
+ drm_intel_gem_bo_map_gtt(batch->buf);
+ batch->map = batch->buf->virtual;
+
batch->size = intel->maxBatchSize;
batch->ptr = batch->map;
batch->reserved_space = BATCH_RESERVED;
batch->dirty_state = ~0;
+ batch->state_batch_offset = batch->size;
}
struct intel_batchbuffer *
struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
batch->intel = intel;
- batch->buffer = malloc(intel->maxBatchSize);
intel_batchbuffer_reset(batch);
return batch;
void
intel_batchbuffer_free(struct intel_batchbuffer *batch)
{
- free (batch->buffer);
- drm_intel_bo_unreference(batch->buf);
+ if (batch->map) {
+ drm_intel_gem_bo_unmap_gtt(batch->buf);
+ batch->map = NULL;
+ }
+ dri_bo_unreference(batch->buf);
batch->buf = NULL;
free(batch);
}
int ret = 0;
int x_off = 0, y_off = 0;
- drm_intel_bo_subdata(batch->buf, 0, used, batch->buffer);
+ drm_intel_gem_bo_unmap_gtt(batch->buf);
batch->ptr = NULL;
(x_off & 0xffff) | (y_off << 16));
}
- if (INTEL_DEBUG & DEBUG_BATCH) {
+ if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
drm_intel_bo_map(batch->buf, GL_FALSE);
intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
- intel->intelScreen->deviceID);
+ intel->intelScreen->deviceID, GL_TRUE);
drm_intel_bo_unmap(batch->buf);
if (intel->vtbl.debug_batch != NULL)
if (used == 0)
return;
- if (INTEL_DEBUG & DEBUG_BATCH)
+ if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
used);
do_flush_locked(batch, used);
- if (INTEL_DEBUG & DEBUG_SYNC) {
+ if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
fprintf(stderr, "waiting for idle\n");
drm_intel_bo_map(batch->buf, GL_TRUE);
drm_intel_bo_unmap(batch->buf);
struct intel_context *intel = batch->intel;
if (intel->gen >= 6) {
- BEGIN_BATCH(4);
+ BEGIN_BATCH(8);
+
+ /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+ OUT_BATCH(0); /* write address */
+ OUT_BATCH(0); /* write data */
+
OUT_BATCH(_3DSTATE_PIPE_CONTROL);
OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_WRITE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_NO_WRITE);
OUT_BATCH(0); /* write address */
OUT_BATCH(0); /* write data */