[g3dvl] move z-coord generation for multiple render targets into vertex shader

[mesa.git] / src / mesa / drivers / dri / intel / intel_batchbuffer.c

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index ff741fc39ab28bbba863cea01f65ed980e74015f..4b498f8c5b2b28b77bd69014bc0094b70398cbb6 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -44,7 +44,9 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch)
 
    batch->buf = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
                                   intel->maxBatchSize, 4096);
-   batch->map = batch->buffer;
+   drm_intel_gem_bo_map_gtt(batch->buf);
+   batch->map = batch->buf->virtual;
+
    batch->size = intel->maxBatchSize;
    batch->ptr = batch->map;
    batch->reserved_space = BATCH_RESERVED;
@@ -58,7 +60,6 @@ intel_batchbuffer_alloc(struct intel_context *intel)
    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
 
    batch->intel = intel;
-   batch->buffer = malloc(intel->maxBatchSize);
    intel_batchbuffer_reset(batch);
 
    return batch;
@@ -67,8 +68,11 @@ intel_batchbuffer_alloc(struct intel_context *intel)
 void
 intel_batchbuffer_free(struct intel_batchbuffer *batch)
 {
-   free (batch->buffer);
-   drm_intel_bo_unreference(batch->buf);
+   if (batch->map) {
+      drm_intel_gem_bo_unmap_gtt(batch->buf);
+      batch->map = NULL;
+   }
+   dri_bo_unreference(batch->buf);
    batch->buf = NULL;
    free(batch);
 }
@@ -84,13 +88,7 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
    int ret = 0;
    int x_off = 0, y_off = 0;
 
-   drm_intel_bo_subdata(batch->buf, 0, used, batch->buffer);
-   if (batch->state_batch_offset != batch->size) {
-      drm_intel_bo_subdata(batch->buf,
-                          batch->state_batch_offset,
-                          batch->size - batch->state_batch_offset,
-                          batch->buffer + batch->state_batch_offset);
-   }
+   drm_intel_gem_bo_unmap_gtt(batch->buf);
 
    batch->ptr = NULL;
 
@@ -99,7 +97,7 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
                        (x_off & 0xffff) | (y_off << 16));
    }
 
-   if (INTEL_DEBUG & DEBUG_BATCH) {
+   if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
       drm_intel_bo_map(batch->buf, GL_FALSE);
       intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
                   intel->intelScreen->deviceID, GL_TRUE);
@@ -130,7 +128,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
    if (used == 0)
       return;
 
-   if (INTEL_DEBUG & DEBUG_BATCH)
+   if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
              used);
 
@@ -174,7 +172,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
 
    do_flush_locked(batch, used);
 
-   if (INTEL_DEBUG & DEBUG_SYNC) {
+   if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
       fprintf(stderr, "waiting for idle\n");
       drm_intel_bo_map(batch->buf, GL_TRUE);
       drm_intel_bo_unmap(batch->buf);
@@ -264,10 +262,18 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
    struct intel_context *intel = batch->intel;
 
    if (intel->gen >= 6) {
-      BEGIN_BATCH(4);
+      BEGIN_BATCH(8);
+
+      /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */
+      OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+      OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+      OUT_BATCH(0); /* write address */
+      OUT_BATCH(0); /* write data */
+
       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
       OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
                PIPE_CONTROL_WRITE_FLUSH |
+               PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                PIPE_CONTROL_NO_WRITE);
       OUT_BATCH(0); /* write address */
       OUT_BATCH(0); /* write data */