Merge branch 'remove-copyteximage-hook'

[mesa.git] / src / mesa / drivers / dri / intel / intel_batchbuffer.c

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 77edc3a6bfe8a5d5aac61792f4353ed5820c5b3e..97cc219ce6dbb091f093392de0b9c7d2f7dbb6d9 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -52,6 +52,22 @@ static void clear_cache( struct intel_context *intel )
    intel->batch.cached_items = NULL;
 }
 
+void
+intel_batchbuffer_init(struct intel_context *intel)
+{
+   intel_batchbuffer_reset(intel);
+
+   if (intel->gen == 6) {
+      /* We can't just use brw_state_batch to get a chunk of space for
+       * the gen6 workaround because it involves actually writing to
+       * the buffer, and the kernel doesn't let us write to the batch.
+       */
+      intel->batch.workaround_bo = drm_intel_bo_alloc(intel->bufmgr,
+                                                     "gen6 workaround",
+                                                     4096, 4096);
+   }
+}
+
 void
 intel_batchbuffer_reset(struct intel_context *intel)
 {
@@ -76,6 +92,7 @@ intel_batchbuffer_free(struct intel_context *intel)
 {
    drm_intel_bo_unreference(intel->batch.last_bo);
    drm_intel_bo_unreference(intel->batch.bo);
+   drm_intel_bo_unreference(intel->batch.workaround_bo);
    clear_cache(intel);
 }
 
@@ -110,9 +127,11 @@ do_flush_locked(struct intel_context *intel)
    }
 
    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
-      intel_decode(batch->map, batch->used,
+      drm_intel_bo_map(batch->bo, false);
+      intel_decode(batch->bo->virtual, batch->used,
                   batch->bo->offset,
                   intel->intelScreen->deviceID, GL_TRUE);
+      drm_intel_bo_unmap(batch->bo);
 
       if (intel->vtbl.debug_batch != NULL)
         intel->vtbl.debug_batch(intel);
@@ -276,6 +295,68 @@ emit:
    item->header = intel->batch.emit;
 }
 
+/**
+ * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
+ * implementing two workarounds on gen6.  From section 1.4.7.1
+ * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
+ *
+ * [DevSNB-C+{W/A}] Before any depth stall flush (including those
+ * produced by non-pipelined state commands), software needs to first
+ * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
+ * 0.
+ *
+ * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
+ * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
+ *
+ * And the workaround for these two requires this workaround first:
+ *
+ * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
+ * BEFORE the pipe-control with a post-sync op and no write-cache
+ * flushes.
+ *
+ * And this last workaround is tricky because of the requirements on
+ * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
+ * volume 2 part 1:
+ *
+ *     "1 of the following must also be set:
+ *      - Render Target Cache Flush Enable ([12] of DW1)
+ *      - Depth Cache Flush Enable ([0] of DW1)
+ *      - Stall at Pixel Scoreboard ([1] of DW1)
+ *      - Depth Stall ([13] of DW1)
+ *      - Post-Sync Operation ([13] of DW1)
+ *      - Notify Enable ([8] of DW1)"
+ *
+ * The cache flushes require the workaround flush that triggered this
+ * one, so we can't use it.  Depth stall would trigger the same.
+ * Post-sync nonzero is what triggered this second workaround, so we
+ * can't use that one either.  Notify enable is IRQs, which aren't
+ * really our business.  That leaves only stall at scoreboard.
+ */
+void
+intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
+{
+   if (!intel->batch.need_workaround_flush)
+      return;
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+   OUT_BATCH(PIPE_CONTROL_CS_STALL |
+            PIPE_CONTROL_STALL_AT_SCOREBOARD);
+   OUT_BATCH(0); /* address */
+   OUT_BATCH(0); /* write data */
+   ADVANCE_BATCH();
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+   OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+   OUT_RELOC(intel->batch.workaround_bo,
+            I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
+   OUT_BATCH(0); /* write data */
+   ADVANCE_BATCH();
+
+   intel->batch.need_workaround_flush = false;
+}
+
 /* Emit a pipelined flush to either flush render and texture cache for
  * reading from a FBO-drawn texture, or flush so that frontbuffer
  * render appears on the screen in DRI1.
@@ -294,15 +375,17 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
         OUT_BATCH(0);
         ADVANCE_BATCH();
       } else {
-        BEGIN_BATCH(8);
-        /* XXX workaround: issue any post sync != 0 before write
-         * cache flush = 1
-         */
-        OUT_BATCH(_3DSTATE_PIPE_CONTROL);
-        OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
-        OUT_BATCH(0); /* write address */
-        OUT_BATCH(0); /* write data */
+        if (intel->gen == 6) {
+           /* Hardware workaround: SNB B-Spec says:
+            *
+            * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
+            * Flush Enable =1, a PIPE_CONTROL with any non-zero
+            * post-sync-op is required.
+            */
+           intel_emit_post_sync_nonzero_flush(intel);
+        }
 
+        BEGIN_BATCH(4);
         OUT_BATCH(_3DSTATE_PIPE_CONTROL);
         OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
                   PIPE_CONTROL_WRITE_FLUSH |