i965: Drop the check for YUV constants in the param list.

[mesa.git] / src / mesa / drivers / dri / intel / intel_batchbuffer.c

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 0ea0a4fb0781e566019dc82216652931f495227a..9b39823917243a85cb51e6df425ebe8809280a3b 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -38,17 +38,18 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch)
    struct intel_context *intel = batch->intel;
 
    if (batch->buf != NULL) {
-      dri_bo_unreference(batch->buf);
+      drm_intel_bo_unreference(batch->buf);
       batch->buf = NULL;
    }
 
-   batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer",
-                            intel->maxBatchSize, 4096);
+   batch->buf = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
+                                  intel->maxBatchSize, 4096);
    batch->map = batch->buffer;
    batch->size = intel->maxBatchSize;
    batch->ptr = batch->map;
    batch->reserved_space = BATCH_RESERVED;
    batch->dirty_state = ~0;
+   batch->state_batch_offset = batch->size;
 }
 
 struct intel_batchbuffer *
@@ -67,7 +68,7 @@ void
 intel_batchbuffer_free(struct intel_batchbuffer *batch)
 {
    free (batch->buffer);
-   dri_bo_unreference(batch->buf);
+   drm_intel_bo_unreference(batch->buf);
    batch->buf = NULL;
    free(batch);
 }
@@ -83,18 +84,26 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
    int ret = 0;
    int x_off = 0, y_off = 0;
 
-   dri_bo_subdata (batch->buf, 0, used, batch->buffer);
+   drm_intel_bo_subdata(batch->buf, 0, used, batch->buffer);
+   if (batch->state_batch_offset != batch->size) {
+      drm_intel_bo_subdata(batch->buf,
+                          batch->state_batch_offset,
+                          batch->size - batch->state_batch_offset,
+                          batch->buffer + batch->state_batch_offset);
+   }
 
    batch->ptr = NULL;
 
-   if (!intel->no_hw)
-      dri_bo_exec(batch->buf, used, NULL, 0, (x_off & 0xffff) | (y_off << 16));
+   if (!intel->no_hw) {
+      drm_intel_bo_exec(batch->buf, used, NULL, 0,
+                       (x_off & 0xffff) | (y_off << 16));
+   }
 
    if (INTEL_DEBUG & DEBUG_BATCH) {
-      dri_bo_map(batch->buf, GL_FALSE);
+      drm_intel_bo_map(batch->buf, GL_FALSE);
       intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
-                  intel->intelScreen->deviceID);
-      dri_bo_unmap(batch->buf);
+                  intel->intelScreen->deviceID, GL_TRUE);
+      drm_intel_bo_unmap(batch->buf);
 
       if (intel->vtbl.debug_batch != NULL)
         intel->vtbl.debug_batch(intel);
@@ -167,8 +176,8 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
 
    if (INTEL_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "waiting for idle\n");
-      dri_bo_map(batch->buf, GL_TRUE);
-      dri_bo_unmap(batch->buf);
+      drm_intel_bo_map(batch->buf, GL_TRUE);
+      drm_intel_bo_unmap(batch->buf);
    }
 
    /* Reset the buffer:
@@ -181,7 +190,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
  */
 GLboolean
 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
-                             dri_bo *buffer,
+                             drm_intel_bo *buffer,
                              uint32_t read_domains, uint32_t write_domain,
                             uint32_t delta)
 {
@@ -192,8 +201,9 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
    if (batch->ptr - batch->map > batch->buf->size)
     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
            batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
-   ret = dri_bo_emit_reloc(batch->buf, read_domains, write_domain,
-                          delta, batch->ptr - batch->map, buffer);
+   ret = drm_intel_bo_emit_reloc(batch->buf, batch->ptr - batch->map,
+                                buffer, delta,
+                                read_domains, write_domain);
 
    /*
     * Using the old buffer offset, write in what the right data would be, in case
@@ -254,10 +264,18 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
    struct intel_context *intel = batch->intel;
 
    if (intel->gen >= 6) {
-      BEGIN_BATCH(4);
+      BEGIN_BATCH(8);
+
+      /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */
+      OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+      OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+      OUT_BATCH(0); /* write address */
+      OUT_BATCH(0); /* write data */
+
       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
       OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
                PIPE_CONTROL_WRITE_FLUSH |
+               PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                PIPE_CONTROL_NO_WRITE);
       OUT_BATCH(0); /* write address */
       OUT_BATCH(0); /* write data */