i965: Drop the check for YUV constants in the param list.

[mesa.git] / src / mesa / drivers / dri / intel / intel_batchbuffer.c

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 698445c52680c5b36184c71f2822ac893e75ba62..9b39823917243a85cb51e6df425ebe8809280a3b 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -102,7 +102,7 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
    if (INTEL_DEBUG & DEBUG_BATCH) {
       drm_intel_bo_map(batch->buf, GL_FALSE);
       intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
-                  intel->intelScreen->deviceID);
+                  intel->intelScreen->deviceID, GL_TRUE);
       drm_intel_bo_unmap(batch->buf);
 
       if (intel->vtbl.debug_batch != NULL)
@@ -264,10 +264,18 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
    struct intel_context *intel = batch->intel;
 
    if (intel->gen >= 6) {
-      BEGIN_BATCH(4);
+      BEGIN_BATCH(8);
+
+      /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */
+      OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+      OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+      OUT_BATCH(0); /* write address */
+      OUT_BATCH(0); /* write data */
+
       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
       OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
                PIPE_CONTROL_WRITE_FLUSH |
+               PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                PIPE_CONTROL_NO_WRITE);
       OUT_BATCH(0); /* write address */
       OUT_BATCH(0); /* write data */