batch->buf = NULL;
}
- if (!batch->buffer)
- batch->buffer = malloc (intel->maxBatchSize);
-
batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer",
intel->maxBatchSize, 4096);
- if (batch->buffer)
- batch->map = batch->buffer;
- else {
- dri_bo_map(batch->buf, GL_TRUE);
- batch->map = batch->buf->virtual;
- }
+ batch->map = batch->buffer;
batch->size = intel->maxBatchSize;
batch->ptr = batch->map;
+ batch->reserved_space = BATCH_RESERVED;
batch->dirty_state = ~0;
}
struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
batch->intel = intel;
+ batch->buffer = malloc(intel->maxBatchSize);
intel_batchbuffer_reset(batch);
return batch;
void
intel_batchbuffer_free(struct intel_batchbuffer *batch)
{
- if (batch->buffer)
- free (batch->buffer);
- else {
- if (batch->map) {
- dri_bo_unmap(batch->buf);
- batch->map = NULL;
- }
- }
+ free (batch->buffer);
dri_bo_unreference(batch->buf);
batch->buf = NULL;
free(batch);
int ret = 0;
int x_off = 0, y_off = 0;
- if (batch->buffer)
- dri_bo_subdata (batch->buf, 0, used, batch->buffer);
- else
- dri_bo_unmap(batch->buf);
+ dri_bo_subdata (batch->buf, 0, used, batch->buffer);
- batch->map = NULL;
batch->ptr = NULL;
if (!intel->no_hw)
struct intel_context *intel = batch->intel;
GLuint used = batch->ptr - batch->map;
- if (!intel->using_dri2_swapbuffers &&
- intel->first_post_swapbuffers_batch == NULL) {
+ if (intel->first_post_swapbuffers_batch == NULL) {
intel->first_post_swapbuffers_batch = intel->batch->buf;
drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
}
/* Check that we didn't just wrap our batchbuffer at a bad time. */
assert(!intel->no_batch_wrap);
- batch->reserved_space = BATCH_RESERVED;
-
/* TODO: Just pass the relocation list and dma buffer up to the
* kernel.
*/
{
struct intel_context *intel = batch->intel;
- if (intel->gen >= 4) {
+ if (intel->gen >= 6) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
+ PIPE_CONTROL_WRITE_FLUSH |
+ PIPE_CONTROL_NO_WRITE);
+ OUT_BATCH(0); /* write address */
+ OUT_BATCH(0); /* write data */
+ ADVANCE_BATCH();
+ } else if (intel->gen >= 4) {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
- PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_NO_WRITE);
OUT_BATCH(0); /* write address */