mesa: s/CALLOC/calloc/

[mesa.git] / src / mesa / drivers / dri / intel / intel_batchbuffer.h

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index a0a5c9841c6a854e063a4ae73c2fc4ed5549d917..b8b60cd862ba206cb5a785c4c849dee5692ab2b6 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -7,13 +7,32 @@
 #include "intel_bufmgr.h"
 #include "intel_reg.h"
 
-#define BATCH_RESERVED 16
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Number of bytes to reserve for commands necessary to complete a batch.
+ *
+ * This includes:
+ * - MI_BATCHBUFFER_END (4 bytes)
+ * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
+ * - Any state emitted by vtbl->finish_batch()
+ *   - On 965+, this means ending occlusion queries (on Gen6, which has the
+ *     most workaround flushes, this can be as much as (4+4+5)*4 = 52 bytes)
+ */
+#define BATCH_RESERVED 60
+
+struct intel_batchbuffer;
 
+void intel_batchbuffer_init(struct intel_context *intel);
 void intel_batchbuffer_reset(struct intel_context *intel);
 void intel_batchbuffer_free(struct intel_context *intel);
+void intel_batchbuffer_save_state(struct intel_context *intel);
+void intel_batchbuffer_reset_to_saved(struct intel_context *intel);
 
-void _intel_batchbuffer_flush(struct intel_context *intel,
-                             const char *file, int line);
+int _intel_batchbuffer_flush(struct intel_context *intel,
+                            const char *file, int line);
 
 #define intel_batchbuffer_flush(intel) \
        _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
@@ -27,17 +46,20 @@ void _intel_batchbuffer_flush(struct intel_context *intel,
 void intel_batchbuffer_data(struct intel_context *intel,
                             const void *data, GLuint bytes, bool is_blit);
 
-GLboolean intel_batchbuffer_emit_reloc(struct intel_context *intel,
+bool intel_batchbuffer_emit_reloc(struct intel_context *intel,
                                        drm_intel_bo *buffer,
                                       uint32_t read_domains,
                                       uint32_t write_domain,
                                       uint32_t offset);
-GLboolean intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
+bool intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
                                              drm_intel_bo *buffer,
                                              uint32_t read_domains,
                                              uint32_t write_domain,
                                              uint32_t offset);
 void intel_batchbuffer_emit_mi_flush(struct intel_context *intel);
+void intel_emit_post_sync_nonzero_flush(struct intel_context *intel);
+void intel_emit_depth_stall_flushes(struct intel_context *intel);
+void gen7_emit_vs_workaround_flush(struct intel_context *intel);
 
 static INLINE uint32_t float_as_int(float f)
 {
@@ -55,10 +77,11 @@ static INLINE uint32_t float_as_int(float f)
  * be passed as structs rather than dwords, but that's a little bit of
  * work...
  */
-static INLINE GLint
+static INLINE unsigned
 intel_batchbuffer_space(struct intel_context *intel)
 {
-   return (intel->batch.state_batch_offset - intel->batch.reserved_space) - intel->batch.used*4;
+   return (intel->batch.state_batch_offset - intel->batch.reserved_space)
+      - intel->batch.used*4;
 }
 
 
@@ -145,4 +168,8 @@ void intel_batchbuffer_cached_advance(struct intel_context *intel);
 #define ADVANCE_BATCH() intel_batchbuffer_advance(intel);
 #define CACHED_BATCH() intel_batchbuffer_cached_advance(intel);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif