i915: Tell the kernel when we actually need fence registers on our BOs.

[mesa.git] / src / mesa / drivers / dri / intel / intel_blit.c

diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 1d099e7c4752d0d1b5fad09b542477e4fd68678e..6d6af8634768056d848dab02e221de6bec3995d2 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -188,14 +188,14 @@ intelEmitCopyBlit(struct intel_context *intel,
    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
    OUT_BATCH((dst_y << 16) | dst_x);
    OUT_BATCH((dst_y2 << 16) | dst_x2);
-   OUT_RELOC(dst_buffer,
-            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-            dst_offset);
+   OUT_RELOC_FENCED(dst_buffer,
+                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                   dst_offset);
    OUT_BATCH((src_y << 16) | src_x);
    OUT_BATCH((uint16_t)src_pitch);
-   OUT_RELOC(src_buffer,
-            I915_GEM_DOMAIN_RENDER, 0,
-            src_offset);
+   OUT_RELOC_FENCED(src_buffer,
+                   I915_GEM_DOMAIN_RENDER, 0,
+                   src_offset);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
@@ -365,9 +365,9 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
       OUT_BATCH(BR13);
       OUT_BATCH((y1 << 16) | x1);
       OUT_BATCH((y2 << 16) | x2);
-      OUT_RELOC(write_buffer,
-               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               0);
+      OUT_RELOC_FENCED(write_buffer,
+                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                      0);
       OUT_BATCH(clear_val);
       ADVANCE_BATCH();
 
@@ -448,9 +448,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    OUT_BATCH(br13);
    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
-   OUT_RELOC(dst_buffer,
-            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-            dst_offset);
+   OUT_RELOC_FENCED(dst_buffer,
+                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                   dst_offset);
    OUT_BATCH(0); /* bg */
    OUT_BATCH(fg_color); /* fg */
    OUT_BATCH(0); /* pattern base addr */