case PCI_CHIP_G41_G:
chipset = "Intel(R) G41";
break;
+ case PCI_CHIP_B43_G:
+ chipset = "Intel(R) B43";
+ break;
case PCI_CHIP_ILD_G:
chipset = "Intel(R) IGDNG_D";
break;
intelInitBufferFuncs(functions);
intelInitPixelFuncs(functions);
intelInitBufferObjectFuncs(functions);
+ intel_init_syncobj_functions(functions);
}
intel->maxBatchSize = BATCH_SZ;
intel->bufmgr = intelScreen->bufmgr;
+
+ if (0) /* for debug */
+ drm_intel_bufmgr_set_debug(intel->bufmgr, 1);
+
intel->ttm = intelScreen->ttm;
if (intel->ttm) {
int bo_reuse_mode;
if (intel->use_texture_tiling &&
!intel->intelScreen->kernel_exec_fencing) {
fprintf(stderr, "No kernel support for execution fencing, "
- "disabling texture tiling");
+ "disabling texture tiling\n");
intel->use_texture_tiling = GL_FALSE;
}
intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
GLboolean
intelUnbindContext(__DRIcontextPrivate * driContextPriv)
{
+ struct intel_context *intel =
+ (struct intel_context *) driContextPriv->driverPrivate;
+
+ /* Deassociate the context with the drawables.
+ */
+ intel->driDrawable = NULL;
+ intel->driReadDrawable = NULL;
+
return GL_TRUE;
}