intel: Mark frontbuffer dirty in intel_prepare_render()

[mesa.git] / src / mesa / drivers / dri / intel / intel_context.c

diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 9077a611328e75c6fb003d37b1b9d410e4ed2290..8a38ac12aa0d8dc7e1fd4f9f2a5c773b3d91ed79 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -159,10 +159,10 @@ intelGetString(GLcontext * ctx, GLenum name)
          chipset = "Intel(R) B43";
          break;
       case PCI_CHIP_ILD_G:
-         chipset = "Intel(R) IGDNG_D";
+         chipset = "Intel(R) Ironlake Desktop";
          break;
       case PCI_CHIP_ILM_G:
-         chipset = "Intel(R) IGDNG_M";
+         chipset = "Intel(R) Ironlake Mobile";
          break;
       default:
          chipset = "Unknown Intel Chipset";
@@ -362,7 +362,7 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
        if (buffers[i].attachment == __DRI_BUFFER_DEPTH)
          depth_region = region;
 
-       intel_renderbuffer_set_region(rb, region);
+       intel_renderbuffer_set_region(intel, rb, region);
        intel_region_release(&region);
 
        if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
@@ -374,7 +374,7 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
                   continue;
 
             intel_region_reference(&stencil_region, region);
-            intel_renderbuffer_set_region(rb, stencil_region);
+            intel_renderbuffer_set_region(intel, rb, stencil_region);
             intel_region_release(&stencil_region);
          }
        }
@@ -403,6 +403,13 @@ intel_prepare_render(struct intel_context *intel)
         intel_update_renderbuffers(driContext, drawable);
       driContext->dri2.read_stamp = drawable->dri2.stamp;
    }
+
+   /* If we're currently rendering to the front buffer, the rendering
+    * that will happen next will probably dirty the front buffer.  So
+    * mark it as dirty here.
+    */
+   if (intel->is_front_buffer_rendering)
+      intel->front_buffer_dirty = GL_TRUE;
 }
 
 void
@@ -494,15 +501,7 @@ intel_flush(GLcontext *ctx, GLboolean needs_mi_flush)
         (*screen->dri2.loader->flushFrontBuffer)(driContext->driDrawablePriv,
                                                  driContext->driDrawablePriv->loaderPrivate);
 
-        /* Only clear the dirty bit if front-buffer rendering is no longer
-         * enabled.  This is done so that the dirty bit can only be set in
-         * glDrawBuffer.  Otherwise the dirty bit would have to be set at
-         * each of N places that do rendering.  This has worse performances,
-         * but it is much easier to get correct.
-         */
-        if (!intel->is_front_buffer_rendering) {
-           intel->front_buffer_dirty = GL_FALSE;
-        }
+        intel->front_buffer_dirty = GL_FALSE;
       }
    }
 }
@@ -586,6 +585,7 @@ intelInitDriverFunctions(struct dd_function_table *functions)
 
 GLboolean
 intelInitContext(struct intel_context *intel,
+                int api,
                  const __GLcontextModes * mesaVis,
                  __DRIcontext * driContextPriv,
                  void *sharedContextPrivate,
@@ -601,8 +601,8 @@ intelInitContext(struct intel_context *intel,
    if (intelScreen->bufmgr == NULL)
       return GL_FALSE;
 
-   if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx,
-                                 functions, (void *) intel)) {
+   if (!_mesa_initialize_context_for_api(&intel->ctx, api, mesaVis, shareCtx,
+                                        functions, (void *) intel)) {
       printf("%s: failed to init mesa context\n", __FUNCTION__);
       return GL_FALSE;
    }
@@ -616,8 +616,16 @@ intelInitContext(struct intel_context *intel,
       intel->gen = 6;
       intel->needs_ff_sync = GL_TRUE;
       intel->has_luminance_srgb = GL_TRUE;
+   } else if (IS_GEN5(intel->intelScreen->deviceID)) {
+      intel->gen = 5;
+      intel->needs_ff_sync = GL_TRUE;
+      intel->has_luminance_srgb = GL_TRUE;
    } else if (IS_965(intel->intelScreen->deviceID)) {
       intel->gen = 4;
+      if (IS_G4X(intel->intelScreen->deviceID)) {
+         intel->has_luminance_srgb = GL_TRUE;
+         intel->is_g4x = GL_TRUE;
+      }
    } else if (IS_9XX(intel->intelScreen->deviceID)) {
       intel->gen = 3;
       if (IS_945(intel->intelScreen->deviceID)) {
@@ -627,15 +635,6 @@ intelInitContext(struct intel_context *intel,
       intel->gen = 2;
    }
 
-   if (IS_IGDNG(intel->intelScreen->deviceID)) {
-      intel->is_ironlake = GL_TRUE;
-      intel->needs_ff_sync = GL_TRUE;
-      intel->has_luminance_srgb = GL_TRUE;
-   } else if (IS_G4X(intel->intelScreen->deviceID)) {
-      intel->has_luminance_srgb = GL_TRUE;
-      intel->is_g4x = GL_TRUE;
-   }
-
    driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
                        sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915");
    if (intelScreen->deviceID == PCI_CHIP_I865_G)
@@ -737,7 +736,16 @@ intelInitContext(struct intel_context *intel,
 
    intel->RenderIndex = ~0;
 
-   intelInitExtensions(ctx);
+   switch (ctx->API) {
+   case API_OPENGL:
+      intelInitExtensions(ctx);
+      break;
+   case API_OPENGLES:
+      break;
+   case API_OPENGLES2:
+      intelInitExtensionsES2(ctx);
+      break;
+   }
 
    INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control);
    if (INTEL_DEBUG & DEBUG_BUFMGR)