i965: Add hardware context support.

[mesa.git] / src / mesa / drivers / dri / intel / intel_context.h

diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index e673a4e88cf5feaa530e0dbc65bac56977e839fe..29ab187c3e749bf1ae9808f606eaccf985800046 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -49,7 +49,6 @@ extern "C" {
 
 #ifdef __cplusplus
        #undef virtual
-}
 #endif
 
 #include "tnl/t_vertex.h"
@@ -117,6 +116,32 @@ struct intel_sync_object {
 
 struct brw_context;
 
+struct intel_batchbuffer {
+   /** Current batchbuffer being queued up. */
+   drm_intel_bo *bo;
+   /** Last BO submitted to the hardware.  Used for glFinish(). */
+   drm_intel_bo *last_bo;
+   /** BO for post-sync nonzero writes for gen6 workaround. */
+   drm_intel_bo *workaround_bo;
+   bool need_workaround_flush;
+
+   struct cached_batch_item *cached_items;
+
+   uint16_t emit, total;
+   uint16_t used, reserved_space;
+   uint32_t map[8192];
+#define BATCH_SZ (8192*sizeof(uint32_t))
+
+   uint32_t state_batch_offset;
+   bool is_blit;
+   bool needs_sol_reset;
+
+   struct {
+      uint16_t used;
+      int reloc_count;
+   } saved;
+};
+
 /**
  * intel_context is derived from Mesa's context class: struct gl_context.
  */
@@ -152,33 +177,14 @@ struct intel_context
       void (*assert_not_dirty) (struct intel_context *intel);
 
       void (*debug_batch)(struct intel_context *intel);
+      void (*annotate_aub)(struct intel_context *intel);
       bool (*render_target_supported)(struct intel_context *intel,
-                                     gl_format format);
+                                     struct gl_renderbuffer *rb);
 
       /** Can HiZ be enabled on a depthbuffer of the given format? */
       bool (*is_hiz_depth_format)(struct intel_context *intel,
                                  gl_format format);
 
-      /**
-       * \name HiZ operations
-       *
-       * See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
-       *   - 7.5.3.1 Depth Buffer Clear
-       *   - 7.5.3.2 Depth Buffer Resolve
-       *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
-       * \{
-       */
-      void (*resolve_hiz_slice)(struct intel_context *intel,
-                               struct intel_mipmap_tree *mt,
-                               uint32_t level,
-                               uint32_t layer);
-
-      void (*resolve_depth_slice)(struct intel_context *intel,
-                                 struct intel_mipmap_tree *mt,
-                                 uint32_t level,
-                                 uint32_t layer);
-      /** \} */
-
       /**
        * Surface state operations (i965+ only)
        * \{
@@ -208,39 +214,20 @@ struct intel_context
    int gen;
    int gt;
    bool needs_ff_sync;
+   bool is_haswell;
    bool is_g4x;
    bool is_945;
    bool has_separate_stencil;
    bool must_use_separate_stencil;
    bool has_hiz;
+   bool has_llc;
+   bool has_swizzling;
 
    int urb_size;
 
-   struct intel_batchbuffer {
-      /** Current batchbuffer being queued up. */
-      drm_intel_bo *bo;
-      /** Last BO submitted to the hardware.  Used for glFinish(). */
-      drm_intel_bo *last_bo;
-      /** BO for post-sync nonzero writes for gen6 workaround. */
-      drm_intel_bo *workaround_bo;
-      bool need_workaround_flush;
-
-      struct cached_batch_item *cached_items;
-
-      uint16_t emit, total;
-      uint16_t used, reserved_space;
-      uint32_t map[8192];
-#define BATCH_SZ (8192*sizeof(uint32_t))
-
-      uint32_t state_batch_offset;
-      bool is_blit;
-      bool needs_sol_reset;
+   drm_intel_context *hw_ctx;
 
-      struct {
-        uint16_t used;
-        int reloc_count;
-      } saved;
-   } batch;
+   struct intel_batchbuffer batch;
 
    drm_intel_bo *first_post_swapbuffers_batch;
    bool need_throttle;
@@ -287,12 +274,6 @@ struct intel_context
    bool always_flush_batch;
    bool always_flush_cache;
 
-   /* 0 - nonconformant, best performance;
-    * 1 - fallback to sw for known conformance bugs
-    * 2 - always fallback to sw
-    */
-   GLuint conformance_mode;
-
    /* State for intelvb.c and inteltris.c.
     */
    GLuint RenderIndex;
@@ -470,6 +451,7 @@ extern int INTEL_DEBUG;
 #define DEBUG_URB       0x800000
 #define DEBUG_VS        0x1000000
 #define DEBUG_CLIP      0x2000000
+#define DEBUG_AUB       0x4000000
 
 #define DBG(...) do {                                          \
        if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG))            \
@@ -609,4 +591,8 @@ is_power_of_two(uint32_t value)
    return (value & (value - 1)) == 0;
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif