uint16_t emit, total;
uint16_t used, reserved_space;
- uint32_t map[8192];
+ uint32_t *map;
+ uint32_t *cpu_map;
#define BATCH_SZ (8192*sizeof(uint32_t))
uint32_t state_batch_offset;
unsigned surf_index);
void (*update_renderbuffer_surface)(struct brw_context *brw,
struct gl_renderbuffer *rb,
+ bool layered,
unsigned unit);
void (*update_null_renderbuffer_surface)(struct brw_context *brw,
unsigned unit);
void (*create_constant_surface)(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
- int width,
- uint32_t *out_offset);
+ uint32_t size,
+ uint32_t *out_offset,
+ bool dword_pitch);
/** \} */
+
+ /**
+ * Send the appropriate state packets to configure depth, stencil, and
+ * HiZ buffers (i965+ only)
+ */
+ void (*emit_depth_stencil_hiz)(struct brw_context *brw,
+ struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_offset,
+ uint32_t depthbuffer_format,
+ uint32_t depth_surface_type,
+ struct intel_mipmap_tree *stencil_mt,
+ bool hiz, bool separate_stencil,
+ uint32_t width, uint32_t height,
+ uint32_t tile_x, uint32_t tile_y);
+
} vtbl;
GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */
GLuint NewGLState;
-
+
dri_bufmgr *bufmgr;
unsigned int maxBatchSize;
int gt;
bool needs_ff_sync;
bool is_haswell;
+ bool is_baytrail;
bool is_g4x;
bool is_945;
bool has_separate_stencil;
bool no_batch_wrap;
bool tnl_pipeline_running; /**< Set while i915's _tnl_run_pipeline. */
+ /**
+ * Set if we're either a debug context or the INTEL_DEBUG=perf environment
+ * variable is set, this is the flag indicating to do expensive work that
+ * might lead to a perf_debug() call.
+ */
+ bool perf_debug;
+
struct
{
GLuint id;
char buffer[4096];
} upload;
+ uint32_t max_gtt_map_object_size;
+
GLuint stats_wm;
/* Offsets of fields within the current vertex:
struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
GLuint vertex_attr_count;
- GLfloat polygon_offset_scale; /* dependent on depth_scale, bpp */
-
bool hw_stencil;
bool hw_stipple;
bool no_rast;
bool always_flush_batch;
bool always_flush_cache;
+ bool disable_throttling;
/* State for intelvb.c and inteltris.c.
*/
*/
bool is_front_buffer_reading;
- /**
- * Count of intel_regions that are mapped.
- *
- * This allows us to assert that no batch buffer is emitted if a
- * region is mapped.
- */
- int num_mapped_regions;
-
- bool use_texture_tiling;
bool use_early_z;
int driFd;
driOptionCache optionCache;
};
-extern char *__progname;
-
-
#define SUBPIXEL_X 0.125
#define SUBPIXEL_Y 0.125
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
-
-/**
- * Align a value up to an alignment value
- *
- * If \c value is not already aligned to the requested alignment value, it
- * will be rounded up.
- *
- * \param value Value to be rounded
- * \param alignment Alignment value to be used. This must be a power of two.
- *
- * \sa ROUND_DOWN_TO()
- */
-#define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
-
/**
* Align a value down to an alignment value
*
*/
#define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
-#define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0)
-
static INLINE uint32_t
U_FIXED(float value, uint32_t frac_bits)
{
#define DEBUG_BLIT 0x8
#define DEBUG_MIPTREE 0x10
#define DEBUG_PERF 0x20
-#define DEBUG_VERBOSE 0x40
#define DEBUG_BATCH 0x80
#define DEBUG_PIXEL 0x100
#define DEBUG_BUFMGR 0x200
#define DEBUG_VERTS 0x8000
#define DEBUG_DRI 0x10000
#define DEBUG_SF 0x20000
-#define DEBUG_SANITY 0x40000
-#define DEBUG_SLEEP 0x80000
#define DEBUG_STATS 0x100000
-#define DEBUG_TILE 0x200000
#define DEBUG_WM 0x400000
#define DEBUG_URB 0x800000
#define DEBUG_VS 0x1000000
#define DEBUG_CLIP 0x2000000
#define DEBUG_AUB 0x4000000
+#define DEBUG_SHADER_TIME 0x8000000
+#define DEBUG_BLORP 0x10000000
+#define DEBUG_NO16 0x20000000
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"
dbg_printf(__VA_ARGS__); \
} while(0)
-#define fallback_debug(...) do { \
- if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
- dbg_printf(__VA_ARGS__); \
-} while(0)
-
#define perf_debug(...) do { \
- if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
- dbg_printf(__VA_ARGS__); \
+ static GLuint msg_id = 0; \
+ if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
+ dbg_printf(__VA_ARGS__); \
+ if (intel->perf_debug) \
+ _mesa_gl_debug(&intel->ctx, &msg_id, \
+ MESA_DEBUG_TYPE_PERFORMANCE, \
+ MESA_DEBUG_SEVERITY_MEDIUM, \
+ __VA_ARGS__); \
} while(0)
+#define WARN_ONCE(cond, fmt...) do { \
+ if (unlikely(cond)) { \
+ static bool _warned = false; \
+ static GLuint msg_id = 0; \
+ if (!_warned) { \
+ fprintf(stderr, "WARNING: "); \
+ fprintf(stderr, fmt); \
+ _warned = true; \
+ \
+ _mesa_gl_debug(ctx, &msg_id, \
+ MESA_DEBUG_TYPE_OTHER, \
+ MESA_DEBUG_SEVERITY_HIGH, fmt); \
+ } \
+ } \
+} while (0)
+
#define PCI_CHIP_845_G 0x2562
#define PCI_CHIP_I830_M 0x3577
#define PCI_CHIP_I855_GM 0x3582
*/
extern bool intelInitContext(struct intel_context *intel,
- int api,
- const struct gl_config * mesaVis,
- __DRIcontext * driContextPriv,
- void *sharedContextPrivate,
- struct dd_function_table *functions);
+ int api,
+ unsigned major_version,
+ unsigned minor_version,
+ const struct gl_config * mesaVis,
+ __DRIcontext * driContextPriv,
+ void *sharedContextPrivate,
+ struct dd_function_table *functions,
+ unsigned *dri_ctx_error);
extern void intelFinish(struct gl_context * ctx);
extern void intel_flush_rendering_to_batch(struct gl_context *ctx);
void intel_prepare_render(struct intel_context *intel);
void
-intel_downsample_for_dri2_flush(struct intel_context *intel,
- __DRIdrawable *drawable);
+intel_resolve_for_dri2_flush(struct intel_context *intel,
+ __DRIdrawable *drawable);
void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
uint32_t buffer_id);
projects / mesa.git / blobdiff