void (*create_constant_surface)(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
- int width,
- uint32_t *out_offset);
+ uint32_t size,
+ uint32_t *out_offset,
+ bool dword_pitch);
/** \} */
+
+ /**
+ * Send the appropriate state packets to configure depth, stencil, and
+ * HiZ buffers (i965+ only)
+ */
+ void (*emit_depth_stencil_hiz)(struct brw_context *brw,
+ struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_offset,
+ uint32_t depthbuffer_format,
+ uint32_t depth_surface_type,
+ struct intel_mipmap_tree *stencil_mt,
+ bool hiz, bool separate_stencil,
+ uint32_t width, uint32_t height,
+ uint32_t tile_x, uint32_t tile_y);
+
} vtbl;
GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */
GLuint NewGLState;
-
+
dri_bufmgr *bufmgr;
unsigned int maxBatchSize;
int gt;
bool needs_ff_sync;
bool is_haswell;
+ bool is_baytrail;
bool is_g4x;
bool is_945;
bool has_separate_stencil;
char buffer[4096];
} upload;
+ uint32_t max_gtt_map_object_size;
+
GLuint stats_wm;
/* Offsets of fields within the current vertex:
bool no_rast;
bool always_flush_batch;
bool always_flush_cache;
+ bool disable_throttling;
/* State for intelvb.c and inteltris.c.
*/
*/
bool is_front_buffer_reading;
- bool use_texture_tiling;
bool use_early_z;
int driFd;
#define DEBUG_CLIP 0x2000000
#define DEBUG_AUB 0x4000000
#define DEBUG_SHADER_TIME 0x8000000
+#define DEBUG_BLORP 0x10000000
#define DEBUG_NO16 0x20000000
#ifdef HAVE_ANDROID_PLATFORM