Merge branch 'lp-offset-twoside'

[mesa.git] / src / mesa / drivers / dri / intel / intel_reg.h

diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index 57ac8f0cc14cb70782717c29c0f6cd33d621a61a..955b100b212e088b921badfebcd397665e42c434 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -55,6 +55,11 @@
  * additional flushing control.
  */
 #define _3DSTATE_PIPE_CONTROL          (CMD_3D | (3 << 27) | (2 << 24) | 2)
+#define PIPE_CONTROL_CS_STALL          (1 << 20)
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET       (1 << 19)
+#define PIPE_CONTROL_TLB_INVALIDATE    (1 << 18)
+#define PIPE_CONTROL_SYNC_GFDT         (1 << 17)
+#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1 << 16)
 #define PIPE_CONTROL_NO_WRITE          (0 << 14)
 #define PIPE_CONTROL_WRITE_IMMEDIATE   (1 << 14)
 #define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14)
@@ -62,7 +67,14 @@
 #define PIPE_CONTROL_DEPTH_STALL       (1 << 13)
 #define PIPE_CONTROL_WRITE_FLUSH       (1 << 12)
 #define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11)
+#define PIPE_CONTROL_TC_FLUSH          (1 << 10) /* GM45+ only */
+#define PIPE_CONTROL_ISP_DIS           (1 << 9)
 #define PIPE_CONTROL_INTERRUPT_ENABLE  (1 << 8)
+/* GT */
+#define PIPE_CONTROL_VF_CACHE_INVALIDATE       (1 << 4)
+#define PIPE_CONTROL_CONST_CACHE_INVALIDATE    (1 << 3)
+#define PIPE_CONTROL_STATE_CACHE_INVALIDATE    (1 << 2)
+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH         (1 << 0)
 #define PIPE_CONTROL_PPGTT_WRITE       (0 << 2)
 #define PIPE_CONTROL_GLOBAL_GTT_WRITE  (1 << 2)
 
@@ -70,8 +82,10 @@
 
 /** @{
  * 915 definitions
+ *
+ * 915 documents say that bits 31:28 and 1 are "undefined, must be zero."
  */
-#define S0_VB_OFFSET_MASK              0xffffffc0
+#define S0_VB_OFFSET_MASK              0x0ffffffc
 #define S0_AUTO_CACHE_INV_DISABLE      (1<<0)
 /** @} */
 
@@ -189,6 +203,19 @@
 
 #define S7_DEPTH_OFFSET_CONST_MASK     ~0
 
+/* p143 */
+#define _3DSTATE_BUF_INFO_CMD  (CMD_3D | (0x1d<<24) | (0x8e<<16) | 1)
+/* Dword 1 */
+#define BUF_3D_ID_COLOR_BACK   (0x3<<24)
+#define BUF_3D_ID_DEPTH        (0x7<<24)
+#define BUF_3D_USE_FENCE       (1<<23)
+#define BUF_3D_TILED_SURFACE   (1<<22)
+#define BUF_3D_TILE_WALK_X     0
+#define BUF_3D_TILE_WALK_Y     (1<<21)
+#define BUF_3D_PITCH(x)         (((x)/4)<<2)
+/* Dword 2 */
+#define BUF_3D_ADDR(x)         ((x) & ~0x3)
+
 /* Primitive dispatch on 830-945 */
 #define _3DPRIMITIVE                   (CMD_3D | (0x1f << 24))
 #define PRIM_INDIRECT            (1<<23)
@@ -224,6 +251,7 @@
 #define XY_DST_TILED           (1 << 11)
 
 /* BR13 */
+#define BR13_8                 (0x0 << 24)
 #define BR13_565               (0x1 << 24)
 #define BR13_8888              (0x3 << 24)