intel: Consistently use no_batch_wrap in intel_context struct.

[mesa.git] / src / mesa / drivers / dri / intel / intel_regions.c

diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 068a3f33797b4c4cedc85551ff8858c11a97d5f5..80975163d479451a7715a43e611a56fa4bb18913 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -196,6 +196,13 @@ intel_region_alloc(struct intel_context *intel,
    else
       height = ALIGN(height, 2);
 
+   /* If we're untiled, we have to align to 2 rows high because the
+    * data port accesses 2x2 blocks even if the bottom row isn't to be
+    * rendered, so failure to align means we could walk off the end of the
+    * GTT and fault.
+    */
+   height = ALIGN(height, 2);
+
    if (expect_accelerated_upload) {
       buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
                                             pitch * cpp * height, 64);
@@ -575,8 +582,7 @@ intel_recreate_static(struct intel_context *intel,
        * instead of which tiling mode it is.  Guess.
        */
       if (region_desc->tiled) {
-        if (IS_965(intel->intelScreen->deviceID) &&
-            region_desc == &intelScreen->depth)
+        if (intel->gen >= 4 && region_desc == &intelScreen->depth)
            region->tiling = I915_TILING_Y;
         else
            region->tiling = I915_TILING_X;