intel: Consistently use no_batch_wrap in intel_context struct.

[mesa.git] / src / mesa / drivers / dri / intel / intel_regions.c

diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 7525cd9c4d7223ebbb20c97559e2fd3681b905d2..80975163d479451a7715a43e611a56fa4bb18913 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -181,6 +181,28 @@ intel_region_alloc(struct intel_context *intel,
    dri_bo *buffer;
    struct intel_region *region;
 
+   /* If we're tiled, our allocations are in 8 or 32-row blocks, so
+    * failure to align our height means that we won't allocate enough pages.
+    *
+    * If we're untiled, we still have to align to 2 rows high because the
+    * data port accesses 2x2 blocks even if the bottom row isn't to be
+    * rendered, so failure to align means we could walk off the end of the
+    * GTT and fault.
+    */
+   if (tiling == I915_TILING_X)
+      height = ALIGN(height, 8);
+   else if (tiling == I915_TILING_Y)
+      height = ALIGN(height, 32);
+   else
+      height = ALIGN(height, 2);
+
+   /* If we're untiled, we have to align to 2 rows high because the
+    * data port accesses 2x2 blocks even if the bottom row isn't to be
+    * rendered, so failure to align means we could walk off the end of the
+    * GTT and fault.
+    */
+   height = ALIGN(height, 2);
+
    if (expect_accelerated_upload) {
       buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
                                             pitch * cpp * height, 64);
@@ -452,6 +474,7 @@ void
 intel_region_cow(struct intel_context *intel, struct intel_region *region)
 {
    struct intel_buffer_object *pbo = region->pbo;
+   GLboolean ok;
 
    intel_region_release_pbo(intel, region);
 
@@ -463,13 +486,14 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
     */
 
    LOCK_HARDWARE(intel);
-   assert(intelEmitCopyBlit(intel,
-                           region->cpp,
-                           region->pitch, pbo->buffer, 0, region->tiling,
-                           region->pitch, region->buffer, 0, region->tiling,
-                           0, 0, 0, 0,
-                           region->pitch, region->height,
-                           GL_COPY));
+   ok = intelEmitCopyBlit(intel,
+                          region->cpp,
+                          region->pitch, pbo->buffer, 0, region->tiling,
+                          region->pitch, region->buffer, 0, region->tiling,
+                          0, 0, 0, 0,
+                          region->pitch, region->height,
+                          GL_COPY);
+   assert(ok);
    UNLOCK_HARDWARE(intel);
 }
 
@@ -558,8 +582,7 @@ intel_recreate_static(struct intel_context *intel,
        * instead of which tiling mode it is.  Guess.
        */
       if (region_desc->tiled) {
-        if (IS_965(intel->intelScreen->deviceID) &&
-            region_desc == &intelScreen->depth)
+        if (intel->gen >= 4 && region_desc == &intelScreen->depth)
            region->tiling = I915_TILING_Y;
         else
            region->tiling = I915_TILING_X;