#include <sys/ioctl.h>
#include <errno.h>
+#include "main/hash.h"
#include "intel_context.h"
#include "intel_regions.h"
#include "intel_blit.h"
#include "intel_buffer_objects.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
-#include "intel_chipset.h"
#define FILE_DEBUG_FLAG DEBUG_REGION
/* XXX: Thread safety?
*/
-GLubyte *
-intel_region_map(struct intel_context *intel, struct intel_region *region)
+void *
+intel_region_map(struct intel_context *intel, struct intel_region *region,
+ GLbitfield mode)
{
- intelFlush(&intel->ctx);
+ /* We have the region->map_refcount controlling mapping of the BO because
+ * in software fallbacks we may end up mapping the same buffer multiple
+ * times on Mesa's behalf, so we refcount our mappings to make sure that
+ * the pointer stays valid until the end of the unmap chain. However, we
+ * must not emit any batchbuffers between the start of mapping and the end
+ * of unmapping, or further use of the map will be incoherent with the GPU
+ * rendering done by that batchbuffer. Hence we assert in
+ * intel_batchbuffer_flush() that that doesn't happen, which means that the
+ * flush is only needed on first map of the buffer.
+ */
+
+ if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
+ if (drm_intel_bo_busy(region->bo)) {
+ perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
+ }
+ }
_DBG("%s %p\n", __FUNCTION__, region);
- if (!region->map_refcount++) {
- if (region->pbo)
- intel_region_cow(intel, region);
+ if (!region->map_refcount) {
+ intel_flush(&intel->ctx);
- if (region->tiling != I915_TILING_NONE &&
- intel->intelScreen->kernel_exec_fencing)
- drm_intel_gem_bo_map_gtt(region->buffer);
+ if (region->tiling != I915_TILING_NONE)
+ drm_intel_gem_bo_map_gtt(region->bo);
else
- dri_bo_map(region->buffer, GL_TRUE);
- region->map = region->buffer->virtual;
+ drm_intel_bo_map(region->bo, true);
+
+ region->map = region->bo->virtual;
+ }
+ if (region->map) {
+ intel->num_mapped_regions++;
+ region->map_refcount++;
}
return region->map;
{
_DBG("%s %p\n", __FUNCTION__, region);
if (!--region->map_refcount) {
- if (region->tiling != I915_TILING_NONE &&
- intel->intelScreen->kernel_exec_fencing)
- drm_intel_gem_bo_unmap_gtt(region->buffer);
+ if (region->tiling != I915_TILING_NONE)
+ drm_intel_gem_bo_unmap_gtt(region->bo);
else
- dri_bo_unmap(region->buffer);
+ drm_intel_bo_unmap(region->bo);
+
region->map = NULL;
+ --intel->num_mapped_regions;
+ assert(intel->num_mapped_regions >= 0);
}
}
static struct intel_region *
-intel_region_alloc_internal(struct intel_context *intel,
+intel_region_alloc_internal(struct intel_screen *screen,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
- dri_bo *buffer)
+ uint32_t tiling, drm_intel_bo *buffer)
{
struct intel_region *region;
- if (buffer == NULL) {
- _DBG("%s <-- NULL\n", __FUNCTION__);
- return NULL;
- }
-
region = calloc(sizeof(*region), 1);
+ if (region == NULL)
+ return region;
+
region->cpp = cpp;
region->width = width;
region->height = height;
region->pitch = pitch;
region->refcount = 1;
- region->buffer = buffer;
-
- /* Default to no tiling */
- region->tiling = I915_TILING_NONE;
- region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
+ region->bo = buffer;
+ region->tiling = tiling;
+ region->screen = screen;
_DBG("%s <-- %p\n", __FUNCTION__, region);
return region;
}
struct intel_region *
-intel_region_alloc(struct intel_context *intel,
+intel_region_alloc(struct intel_screen *screen,
uint32_t tiling,
- GLuint cpp, GLuint width, GLuint height, GLuint pitch,
- GLboolean expect_accelerated_upload)
+ GLuint cpp, GLuint width, GLuint height,
+ bool expect_accelerated_upload)
{
- dri_bo *buffer;
+ drm_intel_bo *buffer;
+ unsigned long flags = 0;
+ unsigned long aligned_pitch;
struct intel_region *region;
- /* If we're tiled, our allocations are in 8 or 32-row blocks, so
- * failure to align our height means that we won't allocate enough pages.
- *
- * If we're untiled, we still have to align to 2 rows high because the
- * data port accesses 2x2 blocks even if the bottom row isn't to be
- * rendered, so failure to align means we could walk off the end of the
- * GTT and fault.
- */
- if (tiling == I915_TILING_X)
- height = ALIGN(height, 8);
- else if (tiling == I915_TILING_Y)
- height = ALIGN(height, 32);
- else
- height = ALIGN(height, 2);
-
- /* If we're untiled, we have to align to 2 rows high because the
- * data port accesses 2x2 blocks even if the bottom row isn't to be
- * rendered, so failure to align means we could walk off the end of the
- * GTT and fault.
- */
- height = ALIGN(height, 2);
-
- if (expect_accelerated_upload) {
- buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
- pitch * cpp * height, 64);
- } else {
- buffer = drm_intel_bo_alloc(intel->bufmgr, "region",
- pitch * cpp * height, 64);
- }
+ if (expect_accelerated_upload)
+ flags |= BO_ALLOC_FOR_RENDER;
- region = intel_region_alloc_internal(intel, cpp, width, height,
- pitch, buffer);
+ buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "region",
+ width, height, cpp,
+ &tiling, &aligned_pitch, flags);
+ if (buffer == NULL)
+ return NULL;
- if (tiling != I915_TILING_NONE) {
- assert(((pitch * cpp) & 127) == 0);
- drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
- drm_intel_bo_get_tiling(buffer, ®ion->tiling, ®ion->bit_6_swizzle);
+ region = intel_region_alloc_internal(screen, cpp, width, height,
+ aligned_pitch / cpp, tiling, buffer);
+ if (region == NULL) {
+ drm_intel_bo_unreference(buffer);
+ return NULL;
}
return region;
}
+bool
+intel_region_flink(struct intel_region *region, uint32_t *name)
+{
+ if (region->name == 0) {
+ if (drm_intel_bo_flink(region->bo, ®ion->name))
+ return false;
+
+ _mesa_HashInsert(region->screen->named_regions,
+ region->name, region);
+ }
+
+ *name = region->name;
+
+ return true;
+}
+
struct intel_region *
-intel_region_alloc_for_handle(struct intel_context *intel,
+intel_region_alloc_for_handle(struct intel_screen *screen,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
GLuint handle, const char *name)
{
- struct intel_region *region;
- dri_bo *buffer;
+ struct intel_region *region, *dummy;
+ drm_intel_bo *buffer;
int ret;
+ uint32_t bit_6_swizzle, tiling;
+
+ region = _mesa_HashLookup(screen->named_regions, handle);
+ if (region != NULL) {
+ dummy = NULL;
+ if (region->width != width || region->height != height ||
+ region->cpp != cpp || region->pitch != pitch) {
+ fprintf(stderr,
+ "Region for name %d already exists but is not compatible\n",
+ handle);
+ return NULL;
+ }
+ intel_region_reference(&dummy, region);
+ return dummy;
+ }
- buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle);
-
- region = intel_region_alloc_internal(intel, cpp,
- width, height, pitch, buffer);
- if (region == NULL)
- return region;
-
- ret = dri_bo_get_tiling(region->buffer, ®ion->tiling,
- ®ion->bit_6_swizzle);
+ buffer = intel_bo_gem_create_from_name(screen->bufmgr, name, handle);
+ if (buffer == NULL)
+ return NULL;
+ ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle);
if (ret != 0) {
fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
handle, name, strerror(-ret));
- intel_region_release(®ion);
+ drm_intel_bo_unreference(buffer);
return NULL;
}
+ region = intel_region_alloc_internal(screen, cpp,
+ width, height, pitch, tiling, buffer);
+ if (region == NULL) {
+ drm_intel_bo_unreference(buffer);
+ return NULL;
+ }
+
+ region->name = handle;
+ _mesa_HashInsert(screen->named_regions, handle, region);
+
return region;
}
void
intel_region_reference(struct intel_region **dst, struct intel_region *src)
{
- if (src)
- _DBG("%s %p %d\n", __FUNCTION__, src, src->refcount);
+ _DBG("%s: %p(%d) -> %p(%d)\n", __FUNCTION__,
+ *dst, *dst ? (*dst)->refcount : 0, src, src ? src->refcount : 0);
- assert(*dst == NULL);
- if (src) {
- src->refcount++;
+ if (src != *dst) {
+ if (*dst)
+ intel_region_release(dst);
+
+ if (src)
+ src->refcount++;
*dst = src;
}
}
if (region->refcount == 0) {
assert(region->map_refcount == 0);
- if (region->pbo)
- region->pbo->region = NULL;
- region->pbo = NULL;
- dri_bo_unreference(region->buffer);
+ drm_intel_bo_unreference(region->bo);
- if (region->classic_map != NULL) {
- drmUnmap(region->classic_map,
- region->pitch * region->cpp * region->height);
- }
+ if (region->name > 0)
+ _mesa_HashRemove(region->screen->named_regions, region->name);
free(region);
}
dst += dst_x * cpp;
src += src_x * cpp;
dst += dst_y * dst_pitch;
- src += src_y * dst_pitch;
+ src += src_y * src_pitch;
width *= cpp;
if (width == dst_pitch && width == src_pitch)
}
}
-
-/* Upload data to a rectangular sub-region. Lots of choices how to do this:
- *
- * - memcpy by span to current destination
- * - upload data as new buffer and blit
- *
- * Currently always memcpy.
- */
-void
-intel_region_data(struct intel_context *intel,
- struct intel_region *dst,
- GLuint dst_offset,
- GLuint dstx, GLuint dsty,
- const void *src, GLuint src_pitch,
- GLuint srcx, GLuint srcy, GLuint width, GLuint height)
-{
- _DBG("%s\n", __FUNCTION__);
-
- if (intel == NULL)
- return;
-
- if (dst->pbo) {
- if (dstx == 0 &&
- dsty == 0 && width == dst->pitch && height == dst->height)
- intel_region_release_pbo(intel, dst);
- else
- intel_region_cow(intel, dst);
- }
-
- _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset,
- dst->cpp,
- dst->pitch,
- dstx, dsty, width, height, src, src_pitch, srcx, srcy);
-
- intel_region_unmap(intel, dst);
-}
-
/* Copy rectangular sub-regions. Need better logic about when to
* push buffers into AGP - will currently do so whenever possible.
*/
-GLboolean
+bool
intel_region_copy(struct intel_context *intel,
struct intel_region *dst,
GLuint dst_offset,
struct intel_region *src,
GLuint src_offset,
GLuint srcx, GLuint srcy, GLuint width, GLuint height,
+ bool flip,
GLenum logicop)
{
+ uint32_t src_pitch = src->pitch;
+
_DBG("%s\n", __FUNCTION__);
if (intel == NULL)
- return GL_FALSE;
-
- if (dst->pbo) {
- if (dstx == 0 &&
- dsty == 0 && width == dst->pitch && height == dst->height)
- intel_region_release_pbo(intel, dst);
- else
- intel_region_cow(intel, dst);
- }
+ return false;
assert(src->cpp == dst->cpp);
+ if (flip)
+ src_pitch = -src_pitch;
+
return intelEmitCopyBlit(intel,
dst->cpp,
- src->pitch, src->buffer, src_offset, src->tiling,
- dst->pitch, dst->buffer, dst_offset, dst->tiling,
+ src_pitch, src->bo, src_offset, src->tiling,
+ dst->pitch, dst->bo, dst_offset, dst->tiling,
srcx, srcy, dstx, dsty, width, height,
logicop);
}
-/* Attach to a pbo, discarding our data. Effectively zero-copy upload
- * the pbo's data.
+/**
+ * This function computes masks that may be used to select the bits of the X
+ * and Y coordinates that indicate the offset within a tile. If the region is
+ * untiled, the masks are set to 0.
*/
void
-intel_region_attach_pbo(struct intel_context *intel,
- struct intel_region *region,
- struct intel_buffer_object *pbo)
+intel_region_get_tile_masks(struct intel_region *region,
+ uint32_t *mask_x, uint32_t *mask_y)
{
- dri_bo *buffer;
-
- if (region->pbo == pbo)
- return;
-
- _DBG("%s %p %p\n", __FUNCTION__, region, pbo);
-
- /* If there is already a pbo attached, break the cow tie now.
- * Don't call intel_region_release_pbo() as that would
- * unnecessarily allocate a new buffer we would have to immediately
- * discard.
- */
- if (region->pbo) {
- region->pbo->region = NULL;
- region->pbo = NULL;
- }
-
- if (region->buffer) {
- dri_bo_unreference(region->buffer);
- region->buffer = NULL;
+ int cpp = region->cpp;
+
+ switch (region->tiling) {
+ default:
+ assert(false);
+ case I915_TILING_NONE:
+ *mask_x = *mask_y = 0;
+ break;
+ case I915_TILING_X:
+ *mask_x = 512 / cpp - 1;
+ *mask_y = 7;
+ break;
+ case I915_TILING_Y:
+ *mask_x = 128 / cpp - 1;
+ *mask_y = 31;
+ break;
}
-
- /* make sure pbo has a buffer of its own */
- buffer = intel_bufferobj_buffer(intel, pbo, INTEL_WRITE_FULL);
-
- region->pbo = pbo;
- region->pbo->region = region;
- dri_bo_reference(buffer);
- region->buffer = buffer;
}
-
-/* Break the COW tie to the pbo and allocate a new buffer.
- * The pbo gets to keep the data.
+/**
+ * Compute the offset (in bytes) from the start of the region to the given x
+ * and y coordinate. For tiled regions, caller must ensure that x and y are
+ * multiples of the tile size.
*/
-void
-intel_region_release_pbo(struct intel_context *intel,
- struct intel_region *region)
+uint32_t
+intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
+ uint32_t y)
{
- _DBG("%s %p\n", __FUNCTION__, region);
- assert(region->buffer == region->pbo->buffer);
- region->pbo->region = NULL;
- region->pbo = NULL;
- dri_bo_unreference(region->buffer);
- region->buffer = NULL;
-
- region->buffer = dri_bo_alloc(intel->bufmgr, "region",
- region->pitch * region->cpp * region->height,
- 64);
-}
-
-/* Break the COW tie to the pbo. Both the pbo and the region end up
- * with a copy of the data.
- */
-void
-intel_region_cow(struct intel_context *intel, struct intel_region *region)
-{
- struct intel_buffer_object *pbo = region->pbo;
- GLboolean ok;
-
- intel_region_release_pbo(intel, region);
-
- assert(region->cpp * region->pitch * region->height == pbo->Base.Size);
-
- _DBG("%s %p (%d bytes)\n", __FUNCTION__, region, pbo->Base.Size);
-
- /* Now blit from the texture buffer to the new buffer:
- */
-
- ok = intelEmitCopyBlit(intel,
- region->cpp,
- region->pitch, pbo->buffer, 0, region->tiling,
- region->pitch, region->buffer, 0, region->tiling,
- 0, 0, 0, 0,
- region->pitch, region->height,
- GL_COPY);
- assert(ok);
-}
-
-dri_bo *
-intel_region_buffer(struct intel_context *intel,
- struct intel_region *region, GLuint flag)
-{
- if (region->pbo) {
- if (flag == INTEL_WRITE_PART)
- intel_region_cow(intel, region);
- else if (flag == INTEL_WRITE_FULL)
- intel_region_release_pbo(intel, region);
+ int cpp = region->cpp;
+ uint32_t pitch = region->pitch * cpp;
+
+ switch (region->tiling) {
+ default:
+ assert(false);
+ case I915_TILING_NONE:
+ return y * pitch + x * cpp;
+ case I915_TILING_X:
+ assert((x % (512 / cpp)) == 0);
+ assert((y % 8) == 0);
+ return y * pitch + x / (512 / cpp) * 4096;
+ case I915_TILING_Y:
+ assert((x % (128 / cpp)) == 0);
+ assert((y % 32) == 0);
+ return y * pitch + x / (128 / cpp) * 4096;
}
-
- return region->buffer;
}
projects / mesa.git / blobdiff