i965: Bump kernel requirement to 3.3 on Ivybridge.
[mesa.git] / src / mesa / drivers / dri / intel / intel_screen.c
index ba321bd049797f6b770a7764f99ad9585522a5e9..433f4ed2bd3d464a3e905e956077388a75030e4a 100644 (file)
@@ -34,7 +34,6 @@
 #include "main/texobj.h"
 #include "main/hash.h"
 #include "main/fbobject.h"
-#include "main/mfeatures.h"
 #include "main/version.h"
 #include "swrast/s_renderbuffer.h"
 
@@ -55,46 +54,35 @@ PUBLIC const char __driConfigOptions[] =
         DRI_CONF_DESC_END
       DRI_CONF_OPT_END
 
-      DRI_CONF_OPT_BEGIN(texture_tiling, bool, true)
-        DRI_CONF_DESC(en, "Enable texture tiling")
-      DRI_CONF_OPT_END
-
-      DRI_CONF_OPT_BEGIN(hiz, bool, true)
+      DRI_CONF_OPT_BEGIN_B(hiz, "true")
         DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+")
       DRI_CONF_OPT_END
 
-      DRI_CONF_OPT_BEGIN(early_z, bool, false)
+      DRI_CONF_OPT_BEGIN_B(early_z, "false")
         DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).")
       DRI_CONF_OPT_END
 
-      DRI_CONF_OPT_BEGIN(fragment_shader, bool, true)
-        DRI_CONF_DESC(en, "Enable limited ARB_fragment_shader support on 915/945.")
-      DRI_CONF_OPT_END
-
    DRI_CONF_SECTION_END
    DRI_CONF_SECTION_QUALITY
-      DRI_CONF_FORCE_S3TC_ENABLE(false)
+      DRI_CONF_FORCE_S3TC_ENABLE("false")
       DRI_CONF_ALLOW_LARGE_TEXTURES(2)
    DRI_CONF_SECTION_END
    DRI_CONF_SECTION_DEBUG
-     DRI_CONF_NO_RAST(false)
-     DRI_CONF_ALWAYS_FLUSH_BATCH(false)
-     DRI_CONF_ALWAYS_FLUSH_CACHE(false)
-     DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN(false)
-     DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS(false)
-     DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED(false)
-
-      DRI_CONF_OPT_BEGIN(stub_occlusion_query, bool, false)
-        DRI_CONF_DESC(en, "Enable stub ARB_occlusion_query support on 915/945.")
-      DRI_CONF_OPT_END
-
-      DRI_CONF_OPT_BEGIN(shader_precompile, bool, true)
+      DRI_CONF_NO_RAST("false")
+      DRI_CONF_ALWAYS_FLUSH_BATCH("false")
+      DRI_CONF_ALWAYS_FLUSH_CACHE("false")
+      DRI_CONF_DISABLE_THROTTLING("false")
+      DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
+      DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
+      DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
+
+      DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
         DRI_CONF_DESC(en, "Perform code generation at shader link time.")
       DRI_CONF_OPT_END
    DRI_CONF_SECTION_END
 DRI_CONF_END;
 
-const GLuint __driNConfigOptions = 16;
+const GLuint __driNConfigOptions = 14;
 
 #include "intel_batchbuffer.h"
 #include "intel_buffers.h"
@@ -371,6 +359,9 @@ intel_create_image_from_name(__DRIscreen *screen,
     int cpp;
 
     image = intel_allocate_image(format, loaderPrivate);
+    if (image == NULL)
+       return NULL;
+
     if (image->format == MESA_FORMAT_NONE)
        cpp = 1;
     else
@@ -418,6 +409,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
    image->dri_format = intel_dri_format(image->format);
    image->has_depthstencil = irb->mt->stencil_mt? true : false;
 
+   rb->NeedsFinishRenderTexture = true;
    return image;
 }
 
@@ -507,6 +499,9 @@ intel_create_image(__DRIscreen *screen,
    }
 
    image = intel_allocate_image(format, loaderPrivate);
+   if (image == NULL)
+      return NULL;
+
    cpp = _mesa_get_format_bytes(image->format);
    image->region =
       intel_region_alloc(intelScreen, tiling, cpp, width, height, true);
@@ -546,6 +541,10 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
          return false;
       *value = image->planar_format->components;
       return true;
+   case __DRI_IMAGE_ATTRIB_FD:
+      if (drm_intel_bo_gem_export_to_prime(image->region->bo, value) == 0)
+         return true;
+      return false;
   default:
       return false;
    }
@@ -623,8 +622,8 @@ intel_create_image_from_names(__DRIscreen *screen,
                                          names[0], strides[0],
                                          loaderPrivate);
 
-    if (image == NULL)
-        return NULL;
+   if (image == NULL)
+      return NULL;
 
     image->planar_format = f;
     for (i = 0; i < f->nplanes; i++) {
@@ -636,6 +635,52 @@ intel_create_image_from_names(__DRIscreen *screen,
     return image;
 }
 
+static __DRIimage *
+intel_create_image_from_fds(__DRIscreen *screen,
+                            int width, int height, int fourcc,
+                            int *fds, int num_fds, int *strides, int *offsets,
+                            void *loaderPrivate)
+{
+   struct intel_screen *intelScreen = screen->driverPrivate;
+   struct intel_image_format *f = NULL;
+   __DRIimage *image;
+   int i, index;
+
+   if (fds == NULL || num_fds != 1)
+      return NULL;
+
+   for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
+      if (intel_image_formats[i].fourcc == fourcc) {
+         f = &intel_image_formats[i];
+      }
+   }
+
+   if (f == NULL)
+      return NULL;
+
+   image = intel_allocate_image(__DRI_IMAGE_FORMAT_NONE, loaderPrivate);
+   if (image == NULL)
+      return NULL;
+
+   image->region = intel_region_alloc_for_fd(intelScreen,
+                                             1, width, height,
+                                             strides[0], fds[0], "image");
+   if (image->region == NULL) {
+      free(image);
+      return NULL;
+   }
+
+   image->planar_format = f;
+   for (i = 0; i < f->nplanes; i++) {
+      index = f->planes[i].buffer_index;
+      image->offsets[index] = offsets[index];
+      image->strides[index] = strides[index];
+   }
+
+   return image;
+}
+
+
 static __DRIimage *
 intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
 {
@@ -660,6 +705,9 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
     stride = parent->strides[index];
 
     image = intel_allocate_image(dri_format, loaderPrivate);
+    if (image == NULL)
+       return NULL;
+
     if (offset + height * stride > parent->region->bo->size) {
        _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
        free(image);
@@ -680,7 +728,6 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
     image->region->bo = parent->region->bo;
     drm_intel_bo_reference(image->region->bo);
     image->region->tiling = parent->region->tiling;
-    image->region->screen = parent->region->screen;
     image->offset = offset;
     intel_setup_image_from_dimensions(image);
 
@@ -693,7 +740,7 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
 }
 
 static struct __DRIimageExtensionRec intelImageExtension = {
-    .base = { __DRI_IMAGE, 6 },
+    .base = { __DRI_IMAGE, 7 },
 
     .createImageFromName                = intel_create_image_from_name,
     .createImageFromRenderbuffer        = intel_create_image_from_renderbuffer,
@@ -704,7 +751,8 @@ static struct __DRIimageExtensionRec intelImageExtension = {
     .validateUsage                      = intel_validate_usage,
     .createImageFromNames               = intel_create_image_from_names,
     .fromPlanar                         = intel_from_planar,
-    .createImageFromTexture             = intel_create_image_from_texture
+    .createImageFromTexture             = intel_create_image_from_texture,
+    .createImageFromFds                 = intel_create_image_from_fds
 };
 
 static const __DRIextension *intelScreenExtensions[] = {
@@ -742,11 +790,6 @@ intel_get_boolean(__DRIscreen *psp, int param)
    return intel_get_param(psp, param, &value) && value;
 }
 
-static void
-nop_callback(GLuint key, void *data, void *userData)
-{
-}
-
 static void
 intelDestroyScreen(__DRIscreen * sPriv)
 {
@@ -755,12 +798,6 @@ intelDestroyScreen(__DRIscreen * sPriv)
    dri_bufmgr_destroy(intelScreen->bufmgr);
    driDestroyOptionInfo(&intelScreen->optionCache);
 
-   /* Some regions may still have references to them at this point, so
-    * flush the hash table to prevent _mesa_DeleteHashTable() from
-    * complaining about the hash not being empty; */
-   _mesa_HashDeleteAll(intelScreen->named_regions, nop_callback, NULL);
-   _mesa_DeleteHashTable(intelScreen->named_regions);
-
    free(intelScreen);
    sPriv->driverPrivate = NULL;
 }
@@ -795,8 +832,15 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
       rgbFormat = MESA_FORMAT_SARGB8;
    else if (mesaVis->alphaBits == 0)
       rgbFormat = MESA_FORMAT_XRGB8888;
-   else
-      rgbFormat = MESA_FORMAT_ARGB8888;
+   else {
+      if (screen->gen >= 4) {
+         rgbFormat = MESA_FORMAT_SARGB8;
+         fb->Visual.sRGBCapable = true;
+      } else {
+         rgbFormat = MESA_FORMAT_ARGB8888;
+      }
+
+   }
 
    /* setup the hardware-based renderbuffers */
    rb = intel_create_renderbuffer(rgbFormat, num_samples);
@@ -942,7 +986,6 @@ static bool
 intel_init_bufmgr(struct intel_screen *intelScreen)
 {
    __DRIscreen *spriv = intelScreen->driScrnPriv;
-   int num_fences = 0;
 
    intelScreen->no_hw = getenv("INTEL_NO_HW") != NULL;
 
@@ -953,19 +996,12 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
       return false;
    }
 
-   if (!intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences) ||
-       num_fences == 0) {
-      fprintf(stderr, "[%s: %u] Kernel 2.6.29 required.\n", __func__, __LINE__);
-      return false;
-   }
-
    drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr);
 
-   intelScreen->named_regions = _mesa_NewHashTable();
-
-   intelScreen->relaxed_relocations = 0;
-   intelScreen->relaxed_relocations |=
-      intel_get_boolean(spriv, I915_PARAM_HAS_RELAXED_DELTA) << 0;
+   if (!intel_get_boolean(spriv, I915_PARAM_HAS_RELAXED_DELTA)) {
+      fprintf(stderr, "[%s: %u] Kernel 2.6.39 required.\n", __func__, __LINE__);
+      return false;
+   }
 
    return true;
 }
@@ -1160,17 +1196,10 @@ set_max_gl_versions(struct intel_screen *screen)
 
    switch (screen->gen) {
    case 7:
-      if (screen->kernel_has_gen7_sol_reset) {
-         screen->max_gl_core_version = 31;
-         screen->max_gl_compat_version = 30;
-         screen->max_gl_es1_version = 11;
-         screen->max_gl_es2_version = 30;
-      } else {
-         screen->max_gl_core_version = 0;
-         screen->max_gl_compat_version = 21;
-         screen->max_gl_es1_version = 11;
-         screen->max_gl_es2_version = 20;
-      }
+      screen->max_gl_core_version = 31;
+      screen->max_gl_compat_version = 30;
+      screen->max_gl_es1_version = 11;
+      screen->max_gl_es2_version = 30;
       break;
    case 6:
       screen->max_gl_core_version = 31;
@@ -1186,23 +1215,10 @@ set_max_gl_versions(struct intel_screen *screen)
       screen->max_gl_es2_version = 20;
       break;
    case 3: {
-      bool has_fragment_shader = driQueryOptionb(&screen->optionCache, "fragment_shader");
-      bool has_occlusion_query = driQueryOptionb(&screen->optionCache, "stub_occlusion_query");
-
       screen->max_gl_core_version = 0;
       screen->max_gl_es1_version = 11;
-
-      if (has_fragment_shader && has_occlusion_query) {
-         screen->max_gl_compat_version = 21;
-      } else {
-         screen->max_gl_compat_version = 14;
-      }
-
-      if (has_fragment_shader) {
-         screen->max_gl_es2_version = 20;
-      } else {
-         screen->max_gl_es2_version = 0;
-      }
+      screen->max_gl_compat_version = 21;
+      screen->max_gl_es2_version = 20;
 
       break;
    }
@@ -1271,10 +1287,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
 
    intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr);
 
-   intelScreen->kernel_has_gen7_sol_reset =
-      intel_get_boolean(intelScreen->driScrnPriv,
-                       I915_PARAM_HAS_GEN7_SOL_RESET);
-
    if (IS_GEN7(intelScreen->deviceID)) {
       intelScreen->gen = 7;
    } else if (IS_GEN6(intelScreen->deviceID)) {
@@ -1289,6 +1301,13 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
       intelScreen->gen = 2;
    }
 
+   if (intelScreen->gen == 7 &&
+       !intel_get_boolean(intelScreen->driScrnPriv,
+                          I915_PARAM_HAS_GEN7_SOL_RESET)) {
+      fprintf(stderr, "i965 requires Kernel 3.3 or later.\n");
+      return false;
+   }
+
    intelScreen->hw_has_separate_stencil = intelScreen->gen >= 6;
    intelScreen->hw_must_use_separate_stencil = intelScreen->gen >= 7;