Merge branch '7.8' into master

[mesa.git] / src / mesa / drivers / dri / intel / intel_screen.c

diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index bc394d048e20460a7eca34605c8478634a515ab3..5e3f40836d04625c56642d2b5c484e779e46a413 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -47,9 +47,6 @@
 #include "i915_drm.h"
 
 #define DRI_CONF_TEXTURE_TILING(def) \
-       DRI_CONF_OPT_BEGIN(texture_tiling, bool, def)           \
-               DRI_CONF_DESC(en, "Enable texture tiling")      \
-       DRI_CONF_OPT_END                                        \
 
 PUBLIC const char __driConfigOptions[] =
    DRI_CONF_BEGIN
@@ -65,11 +62,9 @@ PUBLIC const char __driConfigOptions[] =
         DRI_CONF_DESC_END
       DRI_CONF_OPT_END
 
-#ifdef I915
-     DRI_CONF_TEXTURE_TILING(false)
-#else
-     DRI_CONF_TEXTURE_TILING(true)
-#endif
+      DRI_CONF_OPT_BEGIN(texture_tiling, bool, true)
+        DRI_CONF_DESC(en, "Enable texture tiling")
+      DRI_CONF_OPT_END
 
       DRI_CONF_OPT_BEGIN(early_z, bool, false)
         DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).")
@@ -101,11 +96,6 @@ const GLuint __driNConfigOptions = 11;
 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 #endif /*USE_NEW_INTERFACE */
 
-static const __DRItexOffsetExtension intelTexOffsetExtension = {
-   { __DRI_TEX_OFFSET },
-   intelSetTexOffset,
-};
-
 static const __DRItexBufferExtension intelTexBufferExtension = {
     { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
    intelSetTexBuffer,
@@ -232,7 +222,6 @@ static struct __DRIimageExtensionRec intelImageExtension = {
 
 static const __DRIextension *intelScreenExtensions[] = {
     &driReadDrawableExtension,
-    &intelTexOffsetExtension.base,
     &intelTexBufferExtension.base,
     &intelFlushExtension.base,
     &intelImageExtension.base,
@@ -323,18 +312,13 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
       }
 
       if (mesaVis->depthBits == 24) {
-        if (mesaVis->stencilBits == 8) {
-           /* combined depth/stencil buffer */
-           struct intel_renderbuffer *depthStencilRb
-              = intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
-           /* note: bind RB to two attachment points */
-           _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthStencilRb->Base);
-           _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depthStencilRb->Base);
-        } else {
-           struct intel_renderbuffer *depthRb
-              = intel_create_renderbuffer(MESA_FORMAT_X8_Z24);
-           _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
-        }
+        assert(mesaVis->stencilBits == 8);
+        /* combined depth/stencil buffer */
+        struct intel_renderbuffer *depthStencilRb
+           = intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
+        /* note: bind RB to two attachment points */
+        _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthStencilRb->Base);
+        _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depthStencilRb->Base);
       }
       else if (mesaVis->depthBits == 16) {
          /* just 16-bit depth buffer, no hw stencil */
@@ -421,10 +405,13 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
       return GL_FALSE;
    }
 
-   if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences))
-      intelScreen->kernel_exec_fencing = !!num_fences;
-   else
-      intelScreen->kernel_exec_fencing = GL_FALSE;
+   if (!intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences) ||
+       num_fences == 0) {
+      fprintf(stderr, "[%s: %u] Kernel 2.6.29 required.\n", __func__, __LINE__);
+      return GL_FALSE;
+   }
+
+   drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr);
 
    intelScreen->named_regions = _mesa_NewHashTable();