Merge commit 'origin/master' into drm-gem

[mesa.git] / src / mesa / drivers / dri / intel / intel_screen.c

diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 5233e58fc962b6433318a9a7993f334bfd5b4e72..8fd503ee8b73099940db7427b9724ce07a9dd6de 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -49,7 +49,7 @@
 #include "i830_dri.h"
 #include "intel_regions.h"
 #include "intel_batchbuffer.h"
-#include "intel_bufmgr_ttm.h"
+#include "intel_bufmgr.h"
 
 PUBLIC const char __driConfigOptions[] =
    DRI_CONF_BEGIN
@@ -59,7 +59,7 @@ PUBLIC const char __driConfigOptions[] =
       /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
        * DRI_CONF_BO_REUSE_ALL
        */
-      DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 0, "0:1")
+      DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1")
         DRI_CONF_DESC_BEGIN(en, "Buffer object reuse")
            DRI_CONF_ENUM(0, "Disable buffer object reuse")
            DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
@@ -221,16 +221,16 @@ intelPrintSAREA(const struct drm_i915_sarea * sarea)
            sarea->height);
    fprintf(stderr, "SAREA: pitch: %d\n", sarea->pitch);
    fprintf(stderr,
-           "SAREA: front offset: 0x%08x  size: 0x%x  handle: 0x%x\n",
+           "SAREA: front offset: 0x%08x  size: 0x%x  handle: 0x%x tiled: %d\n",
            sarea->front_offset, sarea->front_size,
-           (unsigned) sarea->front_handle);
+           (unsigned) sarea->front_handle, sarea->front_tiled);
    fprintf(stderr,
-           "SAREA: back  offset: 0x%08x  size: 0x%x  handle: 0x%x\n",
+           "SAREA: back  offset: 0x%08x  size: 0x%x  handle: 0x%x tiled: %d\n",
            sarea->back_offset, sarea->back_size,
-           (unsigned) sarea->back_handle);
-   fprintf(stderr, "SAREA: depth offset: 0x%08x  size: 0x%x  handle: 0x%x\n",
+           (unsigned) sarea->back_handle, sarea->back_tiled);
+   fprintf(stderr, "SAREA: depth offset: 0x%08x  size: 0x%x  handle: 0x%x tiled: %d\n",
            sarea->depth_offset, sarea->depth_size,
-           (unsigned) sarea->depth_handle);
+           (unsigned) sarea->depth_handle, sarea->depth_tiled);
    fprintf(stderr, "SAREA: tex   offset: 0x%08x  size: 0x%x  handle: 0x%x\n",
            sarea->tex_offset, sarea->tex_size, (unsigned) sarea->tex_handle);
 }
@@ -531,20 +531,23 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
 
       /* setup the hardware-based renderbuffers */
       {
-         intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat);
+         intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat, 
+                                                          screen->ttm ? screen->front.tiled : INTEL_TILE_NONE);
          _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
                                &intel_fb->color_rb[0]->Base);
       }
 
       if (mesaVis->doubleBufferMode) {
-         intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat);
+         intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat,
+                                                          screen->ttm ? screen->back.tiled : INTEL_TILE_NONE);
          _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
                                &intel_fb->color_rb[1]->Base);
 
         if (screen->third.handle) {
            struct gl_renderbuffer *tmp_rb = NULL;
 
-           intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat);
+           intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat,
+                                                             screen->ttm ? screen->third.tiled : INTEL_TILE_NONE);
            _mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base);
         }
       }
@@ -553,7 +556,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
         if (mesaVis->stencilBits == 8) {
            /* combined depth/stencil buffer */
            struct intel_renderbuffer *depthStencilRb
-              = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT);
+              = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT,
+                                          screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
            /* note: bind RB to two attachment points */
            _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
                                   &depthStencilRb->Base);
@@ -561,7 +565,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
                                   &depthStencilRb->Base);
         } else {
            struct intel_renderbuffer *depthRb
-              = intel_create_renderbuffer(GL_DEPTH_COMPONENT24);
+              = intel_create_renderbuffer(GL_DEPTH_COMPONENT24,
+                                          screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
            _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
                                   &depthRb->Base);
         }
@@ -569,7 +574,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
       else if (mesaVis->depthBits == 16) {
          /* just 16-bit depth buffer, no hw stencil */
          struct intel_renderbuffer *depthRb
-            = intel_create_renderbuffer(GL_DEPTH_COMPONENT16);
+            = intel_create_renderbuffer(GL_DEPTH_COMPONENT16,
+                                       screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
          _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base);
       }