Merge commit 'origin/st-shader-varients'
[mesa.git] / src / mesa / drivers / dri / intel / intel_span.c
index 8df49908806e0d60ded6c7fc07488b87cc3919d1..2c89a66a95fda430a09a683cf3888c506575fe7e 100644 (file)
@@ -29,7 +29,6 @@
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "main/colormac.h"
-#include "main/texformat.h"
 
 #include "intel_buffers.h"
 #include "intel_fbo.h"
@@ -132,18 +131,6 @@ pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
    dri_bo_subdata(irb->region->buffer, offset, 1, &val);
 }
 
-static uint32_t
-z24s8_to_s8z24(uint32_t val)
-{
-   return (val << 24) | (val >> 8);
-}
-
-static uint32_t
-s8z24_to_z24s8(uint32_t val)
-{
-   return (val >> 24) | (val << 8);
-}
-
 static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
                                int x, int y)
 {
@@ -163,6 +150,9 @@ static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
        int     x_tile_number, y_tile_number;
        int     tile_off, tile_base;
        
+        x += irb->region->draw_x;
+        y += irb->region->draw_y;
+
        tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
 
        xbyte = x * irb->region->cpp;
@@ -218,6 +208,9 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
        int     x_tile_number, y_tile_number;
        int     tile_off, tile_base;
        
+        x += irb->region->draw_x;
+        y += irb->region->draw_y;
+
        tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
 
        xbyte = x * irb->region->cpp;
@@ -273,8 +266,11 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
    unsigned int num_cliprects;                                         \
    struct drm_clip_rect *cliprects;                                    \
    int x_off, y_off;                                                   \
+   int pitch = irb->region->pitch * irb->region->cpp;                  \
+   void *buf = irb->region->buffer->virtual;                           \
    GLuint p;                                                           \
    (void) p;                                                           \
+   (void)buf; (void)pitch; /* unused for non-gttmap. */                        \
    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 
 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
@@ -296,7 +292,6 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 
 #define Y_FLIP(_y) ((_y) * yScale + yBias)
 
-/* XXX with GEM, these need to tell the kernel */
 #define HW_LOCK()
 
 #define HW_UNLOCK()
@@ -354,6 +349,9 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
    unsigned int num_cliprects;                                         \
    struct drm_clip_rect *cliprects;                                    \
    int x_off, y_off;                                                   \
+   int pitch = irb->region->pitch * irb->region->cpp;                  \
+   void *buf = irb->region->buffer->virtual;                           \
+   (void)buf; (void)pitch; /* unused for non-gttmap. */                        \
    intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
 
 
@@ -366,20 +364,22 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 #define INTEL_TAG(name) name##_z16
 #include "intel_depthtmp.h"
 
-/* z24 depthbuffer functions. */
+/* z24x8 depthbuffer functions. */
 #define INTEL_VALUE_TYPE GLuint
 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
-#define INTEL_TAG(name) name##_z24
+#define INTEL_TAG(name) name##_z24_x8
 #include "intel_depthtmp.h"
 
-/* z24s8 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLuint
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
-#define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
-#define INTEL_TAG(name) name##_z24_s8
-#include "intel_depthtmp.h"
 
+/**
+ ** 8-bit stencil function (XXX FBO: This is obsolete)
+ **/
+/* XXX */
+#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
+#define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
+#define TAG(x) intel_gttmap_##x##_z24_s8
+#include "stenciltmp.h"
 
 /**
  ** 8-bit stencil function (XXX FBO: This is obsolete)
@@ -413,6 +413,9 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
    if (irb == NULL || irb->region == NULL)
       return;
 
+   if (intel->intelScreen->kernel_exec_fencing)
+      drm_intel_gem_bo_map_gtt(irb->region->buffer);
+
    intel_set_span_functions(intel, rb);
 }
 
@@ -425,7 +428,10 @@ intel_renderbuffer_unmap(struct intel_context *intel,
    if (irb == NULL || irb->region == NULL)
       return;
 
-   clear_span_cache(irb);
+   if (intel->intelScreen->kernel_exec_fencing)
+      drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
+   else
+      clear_span_cache(irb);
 
    rb->GetRow = NULL;
    rb->PutRow = NULL;
@@ -444,23 +450,30 @@ intel_renderbuffer_unmap(struct intel_context *intel,
  * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
  */
 static void
-intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
+intel_map_unmap_framebuffer(struct intel_context *intel,
+                           struct gl_framebuffer *fb,
+                           GLboolean map)
 {
-   GLcontext *ctx = &intel->ctx;
-   GLuint i, j;
+   GLuint i;
 
    /* color draw buffers */
-   for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
+   for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
       if (map)
-        intel_renderbuffer_map(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
+         intel_renderbuffer_map(intel, fb->_ColorDrawBuffers[i]);
       else
-        intel_renderbuffer_unmap(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
+         intel_renderbuffer_unmap(intel, fb->_ColorDrawBuffers[i]);
    }
 
+   /* color read buffer */
+   if (map)
+      intel_renderbuffer_map(intel, fb->_ColorReadBuffer);
+   else
+      intel_renderbuffer_unmap(intel, fb->_ColorReadBuffer);
+
    /* check for render to textures */
    for (i = 0; i < BUFFER_COUNT; i++) {
       struct gl_renderbuffer_attachment *att =
-         ctx->DrawBuffer->Attachment + i;
+         fb->Attachment + i;
       struct gl_texture_object *tex = att->Texture;
       if (tex) {
          /* render to texture */
@@ -472,33 +485,24 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
       }
    }
 
-   /* color read buffers */
-   if (map)
-      intel_renderbuffer_map(intel, ctx->ReadBuffer->_ColorReadBuffer);
-   else
-      intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
-
    /* depth buffer (Note wrapper!) */
-   if (ctx->DrawBuffer->_DepthBuffer) {
+   if (fb->_DepthBuffer) {
       if (map)
-        intel_renderbuffer_map(intel, ctx->DrawBuffer->_DepthBuffer->Wrapped);
+         intel_renderbuffer_map(intel, fb->_DepthBuffer->Wrapped);
       else
-        intel_renderbuffer_unmap(intel,
-                                 ctx->DrawBuffer->_DepthBuffer->Wrapped);
+         intel_renderbuffer_unmap(intel, fb->_DepthBuffer->Wrapped);
    }
 
    /* stencil buffer (Note wrapper!) */
-   if (ctx->DrawBuffer->_StencilBuffer) {
+   if (fb->_StencilBuffer) {
       if (map)
-        intel_renderbuffer_map(intel,
-                               ctx->DrawBuffer->_StencilBuffer->Wrapped);
+         intel_renderbuffer_map(intel, fb->_StencilBuffer->Wrapped);
       else
-        intel_renderbuffer_unmap(intel,
-                                 ctx->DrawBuffer->_StencilBuffer->Wrapped);
+         intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
    }
-}
-
 
+   intel_check_front_buffer_rendering(intel);
+}
 
 /**
  * Prepare for software rendering.  Map current read/draw framebuffers'
@@ -522,7 +526,9 @@ intelSpanRenderStart(GLcontext * ctx)
       }
    }
 
-   intel_map_unmap_buffers(intel, GL_TRUE);
+   intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_TRUE);
+   if (ctx->ReadBuffer != ctx->DrawBuffer)
+      intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_TRUE);
 }
 
 /**
@@ -544,7 +550,9 @@ intelSpanRenderFinish(GLcontext * ctx)
       }
    }
 
-   intel_map_unmap_buffers(intel, GL_FALSE);
+   intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
+   if (ctx->ReadBuffer != ctx->DrawBuffer)
+      intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
 
    UNLOCK_HARDWARE(intel);
 }
@@ -558,6 +566,43 @@ intelInitSpanFuncs(GLcontext * ctx)
    swdd->SpanRenderFinish = intelSpanRenderFinish;
 }
 
+void
+intel_map_vertex_shader_textures(GLcontext *ctx)
+{
+   struct intel_context *intel = intel_context(ctx);
+   int i;
+
+   if (ctx->VertexProgram._Current == NULL)
+      return;
+
+   for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
+      if (ctx->Texture.Unit[i]._ReallyEnabled &&
+         ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
+         struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
+
+         intel_tex_map_images(intel, intel_texture_object(texObj));
+      }
+   }
+}
+
+void
+intel_unmap_vertex_shader_textures(GLcontext *ctx)
+{
+   struct intel_context *intel = intel_context(ctx);
+   int i;
+
+   if (ctx->VertexProgram._Current == NULL)
+      return;
+
+   for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
+      if (ctx->Texture.Unit[i]._ReallyEnabled &&
+         ctx->VertexProgram._Current->Base.TexturesUsed[i] != 0) {
+         struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
+
+         intel_tex_unmap_images(intel, intel_texture_object(texObj));
+      }
+   }
+}
 
 /**
  * Plug in appropriate span read/write functions for the given renderbuffer.
@@ -568,17 +613,62 @@ intel_set_span_functions(struct intel_context *intel,
                         struct gl_renderbuffer *rb)
 {
    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
-   uint32_t tiling;
+   uint32_t tiling = irb->region->tiling;
+
+   if (intel->intelScreen->kernel_exec_fencing) {
+      switch (irb->texformat) {
+      case MESA_FORMAT_RGB565:
+        intel_gttmap_InitPointers_RGB565(rb);
+        break;
+      case MESA_FORMAT_ARGB4444:
+        intel_gttmap_InitPointers_ARGB4444(rb);
+        break;
+      case MESA_FORMAT_ARGB1555:
+        intel_gttmap_InitPointers_ARGB1555(rb);
+        break;
+      case MESA_FORMAT_XRGB8888:
+         intel_gttmap_InitPointers_xRGB8888(rb);
+        break;
+      case MESA_FORMAT_ARGB8888:
+        if (rb->_BaseFormat == GL_RGB) {
+           /* XXX remove this code someday when we enable XRGB surfaces */
+           /* 8888 RGBx */
+           intel_gttmap_InitPointers_xRGB8888(rb);
+        } else {
+           intel_gttmap_InitPointers_ARGB8888(rb);
+        }
+        break;
+      case MESA_FORMAT_Z16:
+        intel_gttmap_InitDepthPointers_z16(rb);
+        break;
+      case MESA_FORMAT_X8_Z24:
+        intel_gttmap_InitDepthPointers_z24_x8(rb);
+        break;
+      case MESA_FORMAT_S8_Z24:
+        /* There are a few different ways SW asks us to access the S8Z24 data:
+         * Z24 depth-only depth reads
+         * S8Z24 depth reads
+         * S8Z24 stencil reads.
+         */
+        if (rb->Format == MESA_FORMAT_S8_Z24) {
+           intel_gttmap_InitDepthPointers_z24_x8(rb);
+        } else if (rb->Format == MESA_FORMAT_S8) {
+           intel_gttmap_InitStencilPointers_z24_s8(rb);
+        }
+        break;
+      default:
+        _mesa_problem(NULL,
+                      "Unexpected MesaFormat %d in intelSetSpanFunctions",
+                      irb->texformat);
+        break;
+      }
+      return;
+   }
 
    /* If in GEM mode, we need to do the tile address swizzling ourselves,
     * instead of the fence registers handling it.
     */
-   if (intel->ttm)
-      tiling = irb->region->tiling;
-   else
-      tiling = I915_TILING_NONE;
-
-   switch (irb->texformat->MesaFormat) {
+   switch (irb->texformat) {
    case MESA_FORMAT_RGB565:
       switch (tiling) {
       case I915_TILING_NONE:
@@ -621,8 +711,23 @@ intel_set_span_functions(struct intel_context *intel,
         break;
       }
       break;
+   case MESA_FORMAT_XRGB8888:
+      switch (tiling) {
+      case I915_TILING_NONE:
+      default:
+         intelInitPointers_xRGB8888(rb);
+         break;
+      case I915_TILING_X:
+         intel_XTile_InitPointers_xRGB8888(rb);
+         break;
+      case I915_TILING_Y:
+         intel_YTile_InitPointers_xRGB8888(rb);
+         break;
+      }
+      break;
    case MESA_FORMAT_ARGB8888:
-      if (rb->AlphaBits == 0) { /* XXX: Need xRGB8888 Mesa format */
+      if (rb->_BaseFormat == GL_RGB) {
+         /* XXX remove this code someday when we enable XRGB surfaces */
         /* 8888 RGBx */
         switch (tiling) {
         case I915_TILING_NONE:
@@ -666,39 +771,27 @@ intel_set_span_functions(struct intel_context *intel,
         break;
       }
       break;
+   case MESA_FORMAT_X8_Z24:
    case MESA_FORMAT_S8_Z24:
       /* There are a few different ways SW asks us to access the S8Z24 data:
        * Z24 depth-only depth reads
        * S8Z24 depth reads
        * S8Z24 stencil reads.
        */
-      if (rb->_ActualFormat == GL_DEPTH_COMPONENT24) {
+      if (rb->Format == MESA_FORMAT_S8_Z24) {
         switch (tiling) {
         case I915_TILING_NONE:
         default:
-           intelInitDepthPointers_z24(rb);
+           intelInitDepthPointers_z24_x8(rb);
            break;
         case I915_TILING_X:
-           intel_XTile_InitDepthPointers_z24(rb);
+           intel_XTile_InitDepthPointers_z24_x8(rb);
            break;
         case I915_TILING_Y:
-           intel_YTile_InitDepthPointers_z24(rb);
+           intel_YTile_InitDepthPointers_z24_x8(rb);
            break;
         }
-      } else if (rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
-        switch (tiling) {
-        case I915_TILING_NONE:
-        default:
-           intelInitDepthPointers_z24_s8(rb);
-           break;
-        case I915_TILING_X:
-           intel_XTile_InitDepthPointers_z24_s8(rb);
-           break;
-        case I915_TILING_Y:
-           intel_YTile_InitDepthPointers_z24_s8(rb);
-           break;
-        }
-      } else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
+      } else if (rb->Format == MESA_FORMAT_S8) {
         switch (tiling) {
         case I915_TILING_NONE:
         default:
@@ -711,6 +804,9 @@ intel_set_span_functions(struct intel_context *intel,
            intel_YTile_InitStencilPointers_z24_s8(rb);
            break;
         }
+      } else {
+        _mesa_problem(NULL,
+                      "Unexpected ActualFormat in intelSetSpanFunctions");
       }
       break;
    default: