#include "main/macros.h"
#include "main/mtypes.h"
#include "main/colormac.h"
-#include "main/texformat.h"
#include "intel_buffers.h"
#include "intel_fbo.h"
dri_bo_subdata(irb->region->buffer, offset, 1, &val);
}
-static uint32_t
-z24s8_to_s8z24(uint32_t val)
-{
- return (val << 24) | (val >> 8);
-}
-
-static uint32_t
-s8z24_to_z24s8(uint32_t val)
-{
- return (val >> 24) | (val << 8);
-}
-
static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
int x, int y)
{
int x_tile_number, y_tile_number;
int tile_off, tile_base;
+ x += irb->region->draw_x;
+ y += irb->region->draw_y;
+
tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
xbyte = x * irb->region->cpp;
int x_tile_number, y_tile_number;
int tile_off, tile_base;
+ x += irb->region->draw_x;
+ y += irb->region->draw_y;
+
tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
xbyte = x * irb->region->cpp;
unsigned int num_cliprects; \
struct drm_clip_rect *cliprects; \
int x_off, y_off; \
+ int pitch = irb->region->pitch * irb->region->cpp; \
+ void *buf = irb->region->buffer->virtual; \
GLuint p; \
(void) p; \
+ (void)buf; (void)pitch; /* unused for non-gttmap. */ \
intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
/* XXX FBO: this is identical to the macro in spantmp2.h except we get
#define Y_FLIP(_y) ((_y) * yScale + yBias)
-/* XXX with GEM, these need to tell the kernel */
#define HW_LOCK()
#define HW_UNLOCK()
#include "intel_spantmp.h"
/* x8r8g8b8 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
+#define INTEL_PIXEL_FMT GL_BGR
#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
#define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
#define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
unsigned int num_cliprects; \
struct drm_clip_rect *cliprects; \
int x_off, y_off; \
+ int pitch = irb->region->pitch * irb->region->cpp; \
+ void *buf = irb->region->buffer->virtual; \
+ (void)buf; (void)pitch; /* unused for non-gttmap. */ \
intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
#define INTEL_TAG(name) name##_z16
#include "intel_depthtmp.h"
-/* z24 depthbuffer functions. */
+/* z24x8 depthbuffer functions. */
#define INTEL_VALUE_TYPE GLuint
#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
#define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
-#define INTEL_TAG(name) name##_z24
+#define INTEL_TAG(name) name##_z24_x8
#include "intel_depthtmp.h"
-/* z24s8 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLuint
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
-#define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
-#define INTEL_TAG(name) name##_z24_s8
-#include "intel_depthtmp.h"
+/**
+ ** 8-bit stencil function (XXX FBO: This is obsolete)
+ **/
+/* XXX */
+#define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
+#define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
+#define TAG(x) intel_gttmap_##x##_z24_s8
+#include "stenciltmp.h"
/**
** 8-bit stencil function (XXX FBO: This is obsolete)
if (irb == NULL || irb->region == NULL)
return;
+ if (intel->intelScreen->kernel_exec_fencing)
+ drm_intel_gem_bo_map_gtt(irb->region->buffer);
+
intel_set_span_functions(intel, rb);
}
if (irb == NULL || irb->region == NULL)
return;
- clear_span_cache(irb);
+ if (intel->intelScreen->kernel_exec_fencing)
+ drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
+ else
+ clear_span_cache(irb);
rb->GetRow = NULL;
rb->PutRow = NULL;
else
intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped);
}
+
+ intel_check_front_buffer_rendering(intel);
}
/**
GLuint i;
intelFlush(&intel->ctx);
- LOCK_HARDWARE(intel);
for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE);
if (ctx->ReadBuffer != ctx->DrawBuffer)
intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE);
-
- UNLOCK_HARDWARE(intel);
}
struct gl_renderbuffer *rb)
{
struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
- uint32_t tiling;
+ uint32_t tiling = irb->region->tiling;
+
+ if (intel->intelScreen->kernel_exec_fencing) {
+ switch (irb->Base.Format) {
+ case MESA_FORMAT_RGB565:
+ intel_gttmap_InitPointers_RGB565(rb);
+ break;
+ case MESA_FORMAT_ARGB4444:
+ intel_gttmap_InitPointers_ARGB4444(rb);
+ break;
+ case MESA_FORMAT_ARGB1555:
+ intel_gttmap_InitPointers_ARGB1555(rb);
+ break;
+ case MESA_FORMAT_XRGB8888:
+ intel_gttmap_InitPointers_xRGB8888(rb);
+ break;
+ case MESA_FORMAT_ARGB8888:
+ intel_gttmap_InitPointers_ARGB8888(rb);
+ break;
+ case MESA_FORMAT_Z16:
+ intel_gttmap_InitDepthPointers_z16(rb);
+ break;
+ case MESA_FORMAT_X8_Z24:
+ intel_gttmap_InitDepthPointers_z24_x8(rb);
+ break;
+ case MESA_FORMAT_S8_Z24:
+ /* There are a few different ways SW asks us to access the S8Z24 data:
+ * Z24 depth-only depth reads
+ * S8Z24 depth reads
+ * S8Z24 stencil reads.
+ */
+ if (rb->Format == MESA_FORMAT_S8_Z24) {
+ intel_gttmap_InitDepthPointers_z24_x8(rb);
+ } else if (rb->Format == MESA_FORMAT_S8) {
+ intel_gttmap_InitStencilPointers_z24_s8(rb);
+ }
+ break;
+ default:
+ _mesa_problem(NULL,
+ "Unexpected MesaFormat %d in intelSetSpanFunctions",
+ irb->Base.Format);
+ break;
+ }
+ return;
+ }
/* If in GEM mode, we need to do the tile address swizzling ourselves,
* instead of the fence registers handling it.
*/
- if (intel->ttm)
- tiling = irb->region->tiling;
- else
- tiling = I915_TILING_NONE;
-
- switch (irb->texformat->MesaFormat) {
+ switch (irb->Base.Format) {
case MESA_FORMAT_RGB565:
switch (tiling) {
case I915_TILING_NONE:
break;
}
break;
+ case MESA_FORMAT_XRGB8888:
+ switch (tiling) {
+ case I915_TILING_NONE:
+ default:
+ intelInitPointers_xRGB8888(rb);
+ break;
+ case I915_TILING_X:
+ intel_XTile_InitPointers_xRGB8888(rb);
+ break;
+ case I915_TILING_Y:
+ intel_YTile_InitPointers_xRGB8888(rb);
+ break;
+ }
+ break;
case MESA_FORMAT_ARGB8888:
- if (rb->AlphaBits == 0) { /* XXX: Need xRGB8888 Mesa format */
- /* 8888 RGBx */
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitPointers_xRGB8888(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitPointers_xRGB8888(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitPointers_xRGB8888(rb);
- break;
- }
- } else {
- /* 8888 RGBA */
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitPointers_ARGB8888(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitPointers_ARGB8888(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitPointers_ARGB8888(rb);
- break;
- }
+ /* 8888 RGBA */
+ switch (tiling) {
+ case I915_TILING_NONE:
+ default:
+ intelInitPointers_ARGB8888(rb);
+ break;
+ case I915_TILING_X:
+ intel_XTile_InitPointers_ARGB8888(rb);
+ break;
+ case I915_TILING_Y:
+ intel_YTile_InitPointers_ARGB8888(rb);
+ break;
}
break;
case MESA_FORMAT_Z16:
break;
}
break;
+ case MESA_FORMAT_X8_Z24:
case MESA_FORMAT_S8_Z24:
/* There are a few different ways SW asks us to access the S8Z24 data:
* Z24 depth-only depth reads
* S8Z24 depth reads
* S8Z24 stencil reads.
*/
- if (rb->_ActualFormat == GL_DEPTH_COMPONENT24) {
- switch (tiling) {
- case I915_TILING_NONE:
- default:
- intelInitDepthPointers_z24(rb);
- break;
- case I915_TILING_X:
- intel_XTile_InitDepthPointers_z24(rb);
- break;
- case I915_TILING_Y:
- intel_YTile_InitDepthPointers_z24(rb);
- break;
- }
- } else if (rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
+ if (rb->Format == MESA_FORMAT_S8_Z24) {
switch (tiling) {
case I915_TILING_NONE:
default:
- intelInitDepthPointers_z24_s8(rb);
+ intelInitDepthPointers_z24_x8(rb);
break;
case I915_TILING_X:
- intel_XTile_InitDepthPointers_z24_s8(rb);
+ intel_XTile_InitDepthPointers_z24_x8(rb);
break;
case I915_TILING_Y:
- intel_YTile_InitDepthPointers_z24_s8(rb);
+ intel_YTile_InitDepthPointers_z24_x8(rb);
break;
}
- } else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
+ } else if (rb->Format == MESA_FORMAT_S8) {
switch (tiling) {
case I915_TILING_NONE:
default:
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