i965: Always set tiling for depth buffer on sandybridge

[mesa.git] / src / mesa / drivers / dri / intel / intel_tex_copy.c

diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index ddc2c337c8a0f1b6d03df9e89bbcfaa33e9fafd1..6efb2ddc553e21acfaa26462920c2ebf9c89c1a0 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -102,7 +102,7 @@ do_copy_texsubimage(struct intel_context *intel,
    GLcontext *ctx = &intel->ctx;
    const struct intel_region *src = get_teximage_source(intel, internalFormat);
 
-   if (!intelImage->mt || !src) {
+   if (!intelImage->mt || !src || !src->buffer) {
       if (INTEL_DEBUG & DEBUG_FALLBACKS)
         fprintf(stderr, "%s fail %p %p (0x%08x)\n",
                 __FUNCTION__, intelImage->mt, src, internalFormat);
@@ -132,7 +132,7 @@ do_copy_texsubimage(struct intel_context *intel,
                                     0,
                                     &image_x, &image_y);
 
-      /* Can't blit to tiled buffers with non-tile-aligned offset. */
+      /* The blitter can't handle Y-tiled buffers. */
       if (intelImage->mt->region->tiling == I915_TILING_Y) {
         return GL_FALSE;
       }