i965/nir/vec4: Handle uniforms on vertex programs

[mesa.git] / src / mesa / drivers / dri / nouveau / nv10_state_fb.c

diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
index 9badefa3db6aa35b17b39dbaadcb36d33bbdee28..75931849eb9ffd1cde5caf2f14de5e2121cbc640 100644 (file)
--- a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
@@ -40,11 +40,11 @@ get_rt_format(mesa_format format)
                return NV10_3D_RT_FORMAT_COLOR_X8R8G8B8;
        case MESA_FORMAT_B8G8R8A8_UNORM:
                return NV10_3D_RT_FORMAT_COLOR_A8R8G8B8;
-       case MESA_FORMAT_RGB565:
+       case MESA_FORMAT_B5G6R5_UNORM:
                return NV10_3D_RT_FORMAT_COLOR_R5G6B5;
-       case MESA_FORMAT_Z16:
+       case MESA_FORMAT_Z_UNORM16:
                return NV10_3D_RT_FORMAT_DEPTH_Z16;
-       case MESA_FORMAT_Z24_S8:
+       case MESA_FORMAT_S8_UINT_Z24_UNORM:
                return NV10_3D_RT_FORMAT_DEPTH_Z24S8;
        default:
                assert(0);
@@ -106,7 +106,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 
        /* At least nv11 seems to get sad if we don't do this before
         * swapping RTs.*/
-       if (context_chipset(ctx) < 0x17) {
+       if (context_eng3d(ctx)->oclass < NV17_3D_CLASS) {
                int i;
 
                for (i = 0; i < 6; i++) {
@@ -140,7 +140,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
                PUSH_MTHDl(push, NV10_3D(ZETA_OFFSET), BUFCTX_FB,
                                 s->bo, 0, bo_flags);
 
-               if (context_chipset(ctx) >= 0x17) {
+               if (context_eng3d(ctx)->oclass >= NV17_3D_CLASS) {
                        setup_hierz_buffer(ctx);
                        context_dirty(ctx, ZCLEAR);
                }
@@ -152,6 +152,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 
        context_dirty(ctx, VIEWPORT);
        context_dirty(ctx, SCISSOR);
+       context_dirty(ctx, DEPTH);
 }
 
 void