i965/nir: Do not scalarize phis in non-scalar setups
[mesa.git] / src / mesa / drivers / dri / nouveau / nv10_state_raster.c
index bd4a78e1bdb3ac2911f2787acacf4d71ae6656d1..ffde87ab27be4b4096fe329b04a7668378f18f7f 100644 (file)
@@ -28,6 +28,7 @@
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
 #include "nouveau_util.h"
+#include "nv_object.xml.h"
 #include "nv10_3d.xml.h"
 #include "nv10_driver.h"
 
@@ -96,11 +97,12 @@ void
 nv10_emit_depth(struct gl_context *ctx, int emit)
 {
        struct nouveau_pushbuf *push = context_push(ctx);
+       struct gl_framebuffer *fb = ctx->DrawBuffer;
 
        BEGIN_NV04(push, NV10_3D(DEPTH_TEST_ENABLE), 1);
-       PUSH_DATAb(push, ctx->Depth.Test);
+       PUSH_DATAb(push, ctx->Depth.Test && fb->Visual.depthBits > 0);
        BEGIN_NV04(push, NV10_3D(DEPTH_WRITE_ENABLE), 1);
-       PUSH_DATAb(push, ctx->Depth.Mask);
+       PUSH_DATAb(push, ctx->Depth.Mask && fb->Visual.depthBits > 0);
        BEGIN_NV04(push, NV10_3D(DEPTH_FUNC), 1);
        PUSH_DATA (push, nvgl_comparison_op(ctx->Depth.Func));
 }
@@ -120,7 +122,7 @@ nv10_emit_logic_opcode(struct gl_context *ctx, int emit)
        struct nouveau_pushbuf *push = context_push(ctx);
 
        assert(!ctx->Color.ColorLogicOpEnabled
-              || context_chipset(ctx) >= 0x11);
+              || context_eng3d(ctx)->oclass >= NV15_3D_CLASS);
 
        BEGIN_NV04(push, NV11_3D(COLOR_LOGIC_OP_ENABLE), 2);
        PUSH_DATAb(push, ctx->Color.ColorLogicOpEnabled);
@@ -143,7 +145,7 @@ nv10_emit_stencil_func(struct gl_context *ctx, int emit)
        struct nouveau_pushbuf *push = context_push(ctx);
 
        BEGIN_NV04(push, NV10_3D(STENCIL_ENABLE), 1);
-       PUSH_DATAb(push, ctx->Stencil.Enabled);
+       PUSH_DATAb(push, ctx->Stencil._Enabled);
 
        BEGIN_NV04(push, NV10_3D(STENCIL_FUNC_FUNC), 3);
        PUSH_DATA (push, nvgl_comparison_op(ctx->Stencil.Function[0]));