i965/vec4: Generate URB writes using a loop.

[mesa.git] / src / mesa / drivers / dri / r200 / r200_cmdbuf.c

diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index 1d1bea6f5f7fcfe67d7fea0606fd71e5e4b3627b..aa058b39029f0313f4a4f3e53c8baa4bf2e63d1d 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -35,15 +35,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/imports.h"
 #include "main/macros.h"
 #include "main/context.h"
-#include "swrast/swrast.h"
 #include "main/simple_list.h"
 
 #include "radeon_common.h"
 #include "r200_context.h"
-#include "r200_state.h"
 #include "r200_ioctl.h"
-#include "r200_tcl.h"
-#include "r200_sanity.h"
 #include "radeon_reg.h"
 
 /* The state atoms will be emitted in the order they appear in the atom list,
@@ -51,16 +47,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define insert_at_tail_if(atom_list, atom) \
    do { \
-      struct radeon_state_atom* __atom = (atom); \
-      if (__atom->check) \
-        insert_at_tail((atom_list), __atom); \
+      struct radeon_state_atom* current_atom = (atom); \
+      if (current_atom->check) \
+        insert_at_tail((atom_list), current_atom); \
    } while(0)
 
 void r200SetUpAtomList( r200ContextPtr rmesa )
 {
    int i, mtu;
 
-   mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
+   mtu = rmesa->radeon.glCtx.Const.MaxTextureUnits;
 
    make_empty_list(&rmesa->radeon.hw.atomlist);
    rmesa->radeon.hw.atomlist.name = "atom-list";
@@ -92,6 +88,7 @@ void r200SetUpAtomList( r200ContextPtr rmesa )
        insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] );
    insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] );
    insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] );
+   insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.stp );
    for (i = 0; i < 8; ++i)
        insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] );
    for (i = 0; i < 3 + mtu; ++i)
@@ -148,29 +145,19 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
                          R200_VF_COLOR_ORDER_RGBA | 
                          ((vertex_count + 0) << 16) |
                          type);
-               
-               if (!rmesa->radeon.radeonScreen->kernel_mm) {
-                       OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
-                       OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
-                       OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
-                                       rmesa->radeon.tcl.elt_dma_bo,
-                                       rmesa->radeon.tcl.elt_dma_offset,
-                                       RADEON_GEM_DOMAIN_GTT, 0, 0);
-                       OUT_BATCH((vertex_count + 1)/2);
-               } else {
-                       OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
-                       OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
-                       OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
-                       OUT_BATCH((vertex_count + 1)/2);
-                       radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-                                             rmesa->radeon.tcl.elt_dma_bo,
-                                             RADEON_GEM_DOMAIN_GTT, 0, 0);
-               }
+
+               OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
+               OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
+               OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
+               OUT_BATCH((vertex_count + 1)/2);
+               radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+                                     rmesa->radeon.tcl.elt_dma_bo,
+                                     RADEON_GEM_DOMAIN_GTT, 0, 0);
                END_BATCH();
        }
 }
 
-void r200FlushElts(GLcontext *ctx)
+void r200FlushElts(struct gl_context *ctx)
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    int nr, elt_used = rmesa->tcl.elt_used;
@@ -191,11 +178,6 @@ void r200FlushElts(GLcontext *ctx)
 
    if (R200_ELT_BUF_SZ > elt_used)
      radeonReturnDmaRegion(&rmesa->radeon, R200_ELT_BUF_SZ - elt_used);
-
-   if (radeon_is_debug_enabled(RADEON_SYNC, RADEON_CRITICAL)) {
-      radeon_print(RADEON_SYNC, RADEON_NORMAL, "%s: Syncing\n", __FUNCTION__);
-      radeonFinish( rmesa->radeon.glCtx );
-   }
 }
 
 
@@ -219,7 +201,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
    retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
    
    assert(!rmesa->radeon.dma.flush);
-   rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+   rmesa->radeon.glCtx.Driver.NeedFlush |= FLUSH_STORED_VERTICES;
    rmesa->radeon.dma.flush = r200FlushElts;
 
    return retval;
@@ -229,12 +211,10 @@ void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count)
 {
    BATCH_LOCALS(&rmesa->radeon);
 
-   if (rmesa->radeon.radeonScreen->kernel_mm) {
-          BEGIN_BATCH_NO_AUTOSTATE(2);
-          OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));
-          OUT_BATCH(count);
-          END_BATCH();
-   }
+   BEGIN_BATCH_NO_AUTOSTATE(2);
+   OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));
+   OUT_BATCH(count);
+   END_BATCH();
 }
 
 void r200EmitVertexAOS( r200ContextPtr rmesa,
@@ -271,42 +251,7 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
    OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1);
    OUT_BATCH(nr);
 
-    
-   if (!rmesa->radeon.radeonScreen->kernel_mm) {
-      for (i = 0; i + 1 < nr; i += 2) {
-        OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
-                  (rmesa->radeon.tcl.aos[i].stride << 8) |
-                  (rmesa->radeon.tcl.aos[i + 1].components << 16) |
-                  (rmesa->radeon.tcl.aos[i + 1].stride << 24));
-                       
-        voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
-           offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
-        OUT_BATCH_RELOC(voffset,
-                        rmesa->radeon.tcl.aos[i].bo,
-                        voffset,
-                        RADEON_GEM_DOMAIN_GTT,
-                        0, 0);
-        voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
-           offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
-        OUT_BATCH_RELOC(voffset,
-                        rmesa->radeon.tcl.aos[i+1].bo,
-                        voffset,
-                        RADEON_GEM_DOMAIN_GTT,
-                        0, 0);
-      }
-      
-      if (nr & 1) {
-        OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
-                  (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
-        voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
-           offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
-        OUT_BATCH_RELOC(voffset,
-                        rmesa->radeon.tcl.aos[nr - 1].bo,
-                        voffset,
-                        RADEON_GEM_DOMAIN_GTT,
-                        0, 0);
-      }
-   } else {
+   {
       for (i = 0; i + 1 < nr; i += 2) {
         OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
                   (rmesa->radeon.tcl.aos[i].stride << 8) |