fix up radeon span functions using latest r200 code from Brian,

[mesa.git] / src / mesa / drivers / dri / r200 / r200_context.h

diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index eea3a7fe358dc86a4b887e3b9c5c7b81b938baa9..8503070965d584ed11e54594fc23244ca6d57531 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -59,14 +59,12 @@ typedef struct r200_context *r200ContextPtr;
 
 /* Flags for software fallback cases */
 /* See correponding strings in r200_swtcl.c */
-#define R200_FALLBACK_TEXTURE           0x1
-#define R200_FALLBACK_DRAW_BUFFER       0x2
-#define R200_FALLBACK_STENCIL           0x4
-#define R200_FALLBACK_RENDER_MODE       0x8
-#define R200_FALLBACK_BLEND_EQ          0x10
-#define R200_FALLBACK_BLEND_FUNC        0x20
-#define R200_FALLBACK_DISABLE           0x40
-#define R200_FALLBACK_BORDER_MODE       0x80
+#define R200_FALLBACK_TEXTURE           0x01
+#define R200_FALLBACK_DRAW_BUFFER       0x02
+#define R200_FALLBACK_STENCIL           0x04
+#define R200_FALLBACK_RENDER_MODE       0x08
+#define R200_FALLBACK_DISABLE           0x10
+#define R200_FALLBACK_BORDER_MODE       0x20
 
 /* The blit width for texture uploads
  */
@@ -94,7 +92,9 @@ typedef void (*r200_point_func)( r200ContextPtr,
 
 struct r200_colorbuffer_state {
    GLuint clear;
+#if 000
    GLint drawOffset, drawPitch;
+#endif
    int roundEnable;
 };
 
@@ -104,9 +104,11 @@ struct r200_depthbuffer_state {
    GLfloat scale;
 };
 
+#if 000
 struct r200_pixel_state {
    GLint readOffset, readPitch;
 };
+#endif
 
 struct r200_scissor_state {
    drm_clip_rect_t rect;
@@ -174,8 +176,8 @@ struct r200_tex_obj {
 
 struct r200_texture_env_state {
    r200TexObjPtr texobj;
-   GLenum format;
-   GLenum envMode;
+   GLuint outputreg;
+   GLuint unitneeded;
 };
 
 #define R200_MAX_TEXTURE_UNITS 6
@@ -276,12 +278,17 @@ struct r200_state_atom {
 #define TEX_PP_TXSIZE               4  /*2c0c*/
 #define TEX_PP_TXPITCH              5  /*2c10*/
 #define TEX_PP_BORDER_COLOR         6  /*2c14*/
-#define TEX_CMD_1                   7
-#define TEX_PP_TXOFFSET             8  /*2d00 */
-#define TEX_STATE_SIZE              9
-
-#define CUBE_CMD_0                  0  /* 1 register follows */
-#define CUBE_PP_CUBIC_FACES         1  /* 0x2c18 */
+#define TEX_CMD_1_OLDDRM            7
+#define TEX_PP_TXOFFSET_OLDDRM      8  /*2d00 */
+#define TEX_STATE_SIZE_OLDDRM       9
+#define TEX_PP_CUBIC_FACES          7
+#define TEX_PP_TXMULTI_CTL          8
+#define TEX_CMD_1_NEWDRM            9
+#define TEX_PP_TXOFFSET_NEWDRM     10
+#define TEX_STATE_SIZE_NEWDRM      11
+
+#define CUBE_CMD_0                  0  /* 1 register follows */ /* this command unnecessary */
+#define CUBE_PP_CUBIC_FACES         1  /* 0x2c18 */             /* with new enough drm */
 #define CUBE_CMD_1                  2  /* 5 registers follow */
 #define CUBE_PP_CUBIC_OFFSET_F1     3  /* 0x2d04 */
 #define CUBE_PP_CUBIC_OFFSET_F2     4  /* 0x2d08 */
@@ -306,6 +313,25 @@ struct r200_state_atom {
 #define TF_TFACTOR_5                6
 #define TF_STATE_SIZE               7
 
+#define ATF_CMD_0                   0
+#define ATF_TFACTOR_0               1
+#define ATF_TFACTOR_1               2
+#define ATF_TFACTOR_2               3
+#define ATF_TFACTOR_3               4
+#define ATF_TFACTOR_4               5
+#define ATF_TFACTOR_5               6
+#define ATF_TFACTOR_6               7
+#define ATF_TFACTOR_7               8
+#define ATF_STATE_SIZE              9
+
+/* ATI_FRAGMENT_SHADER */
+#define AFS_CMD_0                 0
+#define AFS_IC0                   1 /* 2f00 */
+#define AFS_IC1                   2 /* 2f04 */
+#define AFS_IA0                   3 /* 2f08 */
+#define AFS_IA1                   4 /* 2f0c */
+#define AFS_STATE_SIZE           33
+
 #define TCL_CMD_0                 0
 #define TCL_LIGHT_MODEL_CTL_0     1
 #define TCL_LIGHT_MODEL_CTL_1     2
@@ -371,6 +397,11 @@ struct r200_state_atom {
 #define VTX_STATE_CNTL          8
 #define VTX_STATE_SIZE          9
 
+/* SPR - point sprite state
+ */
+#define SPR_CMD_0             0
+#define SPR_POINT_SPRITE_CNTL 1
+#define SPR_STATE_SIZE        2
 
 #define VTX_COLOR(v,n)   (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\
                          R200_VTX_COLOR_MASK)
@@ -531,6 +562,9 @@ struct r200_hw_state {
    struct r200_state_atom fog;
    struct r200_state_atom glt;
    struct r200_state_atom prf;
+   struct r200_state_atom afs[2];
+   struct r200_state_atom atf;
+   struct r200_state_atom spr;
 
    int max_state_size; /* Number of bytes necessary for a full state emit. */
    GLboolean is_dirty, all_dirty;
@@ -541,11 +575,14 @@ struct r200_state {
     */
    struct r200_colorbuffer_state color;
    struct r200_depthbuffer_state depth;
+#if 00
    struct r200_pixel_state pixel;
+#endif
    struct r200_scissor_state scissor;
    struct r200_stencilbuffer_state stencil;
    struct r200_stipple_state stipple;
    struct r200_texture_state texture;
+   GLuint envneeded;
 };
 
 /* Need refcounting on dma buffers:
@@ -614,7 +651,8 @@ struct r200_tcl_info {
    GLint last_offset;
    GLuint hw_primitive;
 
-   struct r200_dma_region *aos_components[8];
+/* FIXME: what's the maximum number of components? */
+   struct r200_dma_region *aos_components[11];
    GLuint nr_aos_components;
 
    GLuint *Elts;
@@ -914,7 +952,6 @@ struct r200_context {
    GLuint swap_count;
    GLuint swap_missed_count;
 
-   PFNGLXGETUSTPROC get_ust;
 
    /* r200_tcl.c
     */
@@ -938,6 +975,8 @@ struct r200_context {
 
    GLboolean using_hyperz;
    GLboolean texmicrotile;
+
+  struct ati_fragment_shader *afs_loaded;
 };
 
 #define R200_CONTEXT(ctx)              ((r200ContextPtr)(ctx->DriverCtx))