-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_sanity.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
/**************************************************************************
Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
* Keith Whitwell <keith@tungstengraphics.com>
*
*/
-#include <errno.h>
+
+#include <errno.h>
#include "glheader.h"
#include "imports.h"
{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
+ { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
+ { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
+ { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+ { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
+ { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
+ { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
+ { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+ { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
+ { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+ { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
+ { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+ { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" },
+ { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
+ { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
+ { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
+ { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
+ { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
+ { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
+ { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
+ { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
+ { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
};
struct reg_names {
{ R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
{ R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
{ R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
+ { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" },
{ R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
{ R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
{ R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
{ R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
{ R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
{ R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
+ { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" },
{ R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
{ R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
{ R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
{ R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
{ R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
{ R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
+ { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" },
{ R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
{ R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
{ R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
{ R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
{ R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
{ R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
+ { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" },
{ R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
{ R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
{ R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
{ R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
{ R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
{ R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
+ { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" },
{ R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
{ R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
{ R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
{ R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
{ R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
{ R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
+ { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" },
{ R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
{ R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
{ R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
{ R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
{ R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
{ R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
+ { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" },
+ { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" },
{ R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
{ R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
{ R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
{ R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
{ R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
{ R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
+ { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" },
{ R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
{ R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
{ R200_PP_CNTL_X, "R200_PP_CNTL_X" },
- { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
+ { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" },
+ { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" },
+ { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" },
+ { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" },
+ { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" },
+ { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" },
+ { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" },
+ { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" },
+ { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" },
+ { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" },
+ { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" },
+ { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" },
+ { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" },
+ { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" },
+ { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" },
+ { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" },
+ { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" },
+ { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" },
+ { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" },
+ { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" },
+ { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" },
+ { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" },
+ { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" },
+ { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" },
+ { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" },
+ { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" },
+ { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" },
+ { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" },
+ { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" },
+ { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" },
+ { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" },
+ { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" },
+ { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" },
+ { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" },
};
static struct reg_names scalar_names[] = {
}
fprintf(stderr, "*** unknown reg 0x%x\n", reg);
- return 0;
+ return NULL;
}
static int radeon_emit_packets(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int id = (int)header.packet.packet_id;
int sz = packet[id].len;
static int radeon_emit_scalars(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
static int radeon_emit_scalars2(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n",
start, stride, sz, start + stride * sz);
- if (start + stride * sz > 257) {
+ if (start + stride * sz > 258) {
fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz);
return -1;
}
* Check: table start, end, nr, etc.
*/
static int radeon_emit_vectors(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.vectors.count;
int *data = (int *)cmdbuf->buf;
"TRIANGLE_FAN",
"TRIANGLE_STRIP",
"RECT_LIST",
- 0,
+ NULL,
"3VRT_POINTS",
"3VRT_LINES",
"POINT_SPRITES",
/* build in knowledge about each packet type
*/
-static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
{
int cmdsz;
int *cmd = (int *)cmdbuf->buf;
/* Check cliprects for bounds, then pass on to above:
*/
-static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
{
- XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
+ drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes;
int i = 0;
if (VERBOSE && total_changed) {
int r200SanityCmdBuffer( r200ContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes )
+ drm_clip_rect_t *boxes )
{
int idx;
- drmRadeonCmdBuffer cmdbuf;
- drmRadeonCmdHeader header;
+ drm_radeon_cmd_buffer_t cmdbuf;
+ drm_radeon_cmd_header_t header;
static int inited = 0;
if (!inited) {
cmdbuf.buf = rmesa->store.cmd_buf;
cmdbuf.bufsz = rmesa->store.cmd_used;
- cmdbuf.boxes = (drmClipRect *)boxes;
+ cmdbuf.boxes = (drm_clip_rect_t *)boxes;
cmdbuf.nbox = nbox;
while ( cmdbuf.bufsz >= sizeof(header) ) {