-/* $XFree86$ */
/**************************************************************************
Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc, Cedar Park, TX.
+ VMware, Inc.
All Rights Reserved.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ATI, VMWARE AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*
*/
-#include <errno.h>
+
+#include <errno.h>
-#include "glheader.h"
-#include "imports.h"
+#include "main/glheader.h"
+#include "main/imports.h"
#include "r200_context.h"
-#include "r200_ioctl.h"
#include "r200_sanity.h"
#include "radeon_reg.h"
#include "r200_reg.h"
#define MORE_VERBOSE 1
#if MORE_VERBOSE
-#define VERBOSE (R200_DEBUG & DEBUG_VERBOSE)
+#define VERBOSE (R200_DEBUG & RADEON_VERBOSE)
#define NORMAL (1)
#else
#define VERBOSE 0
-#define NORMAL (R200_DEBUG & DEBUG_VERBOSE)
+#define NORMAL (R200_DEBUG & RADEON_VERBOSE)
#endif
{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
+ { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
+ { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
+ { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+ { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
+ { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
+ { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
+ { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+ { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
+ { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+ { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
+ { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+ { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" },
+ { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
+ { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
+ { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
+ { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
+ { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
+ { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
+ { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
+ { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
+ { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
+ { R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
};
struct reg_names {
{ R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
{ R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
{ R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
+ { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" },
{ R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
{ R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
{ R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
{ R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
{ R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
{ R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
+ { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" },
{ R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
{ R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
{ R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
{ R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
{ R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
{ R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
+ { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" },
{ R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
{ R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
{ R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
{ R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
{ R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
{ R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
+ { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" },
{ R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
{ R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
{ R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
{ R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
{ R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
{ R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
+ { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" },
{ R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
{ R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
{ R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
{ R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
{ R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
{ R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
+ { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" },
{ R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
{ R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
{ R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
{ R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
{ R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
{ R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
+ { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" },
+ { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" },
{ R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
{ R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
{ R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
{ R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
{ R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
{ R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
+ { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" },
{ R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
{ R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
{ R200_PP_CNTL_X, "R200_PP_CNTL_X" },
- { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
+ { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" },
+ { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" },
+ { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" },
+ { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" },
+ { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" },
+ { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" },
+ { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" },
+ { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" },
+ { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" },
+ { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" },
+ { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" },
+ { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" },
+ { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" },
+ { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" },
+ { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" },
+ { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" },
+ { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" },
+ { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" },
+ { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" },
+ { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" },
+ { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" },
+ { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" },
+ { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" },
+ { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" },
+ { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" },
+ { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" },
+ { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" },
+ { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" },
+ { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" },
+ { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" },
+ { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" },
+ { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" },
+ { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" },
+ { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" },
+ { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" },
+ { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" },
};
static struct reg_names scalar_names[] = {
{ 1000, "" },
};
-union fi { float f; int i; };
-
#define ISVEC 1
#define ISFLOAT 2
#define TOUCHED 4
};
-static struct reg regs[Elements(reg_names)+1];
+static struct reg regs[ARRAY_SIZE(reg_names)+1];
static struct reg scalars[512+1];
static struct reg vectors[512*4+1];
struct reg_names *tmp;
int i;
- for (i = 0 ; i < Elements(regs) ; i++) {
+ for (i = 0 ; i < ARRAY_SIZE(reg_names) ; i++) {
regs[i].idx = reg_names[i].idx;
regs[i].closest = ®_names[i];
regs[i].flags = 0;
}
- for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) {
+ for (i = 0, tmp = scalar_names ; i < ARRAY_SIZE(scalars) ; i++) {
if (tmp[1].idx == i) tmp++;
scalars[i].idx = i;
scalars[i].closest = tmp;
scalars[i].flags = ISFLOAT;
}
- for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) {
+ for (i = 0, tmp = vector_names ; i < ARRAY_SIZE(vectors) ; i++) {
if (tmp[1].idx*4 == i) tmp++;
vectors[i].idx = i;
vectors[i].closest = tmp;
vectors[i].flags = ISFLOAT|ISVEC;
}
- regs[Elements(regs)-1].idx = -1;
- scalars[Elements(scalars)-1].idx = -1;
- vectors[Elements(vectors)-1].idx = -1;
+ regs[ARRAY_SIZE(regs)-1].idx = -1;
+ scalars[ARRAY_SIZE(scalars)-1].idx = -1;
+ vectors[ARRAY_SIZE(vectors)-1].idx = -1;
}
static int find_or_add_value( struct reg *reg, int val )
if (j == reg->nalloc) {
reg->nalloc += 5;
reg->nalloc *= 2;
- reg->values = (union fi *) realloc( reg->values,
- reg->nalloc * sizeof(union fi) );
+ reg->values = realloc( reg->values, reg->nalloc * sizeof(union fi) );
}
reg->values[reg->nvalues++].i = val;
}
fprintf(stderr, "*** unknown reg 0x%x\n", reg);
- return 0;
+ return NULL;
}
static int print_reg_assignment( struct reg *reg, int data )
{
+ float_ui32_type datau;
+ datau.ui32 = data;
reg->flags |= TOUCHED;
if (reg->flags & ISFLOAT)
- return print_float_reg_assignment( reg, *(float *)&data );
+ return print_float_reg_assignment( reg, datau.f );
else
return print_int_reg_assignment( reg, data );
}
{
int i;
- for (i = 0 ; i < Elements(regs) ; i++)
+ for (i = 0 ; i < ARRAY_SIZE(regs) ; i++)
print_reg( ®s[i] );
- for (i = 0 ; i < Elements(scalars) ; i++)
+ for (i = 0 ; i < ARRAY_SIZE(scalars) ; i++)
print_reg( &scalars[i] );
- for (i = 0 ; i < Elements(vectors) ; i++)
+ for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++)
print_reg( &vectors[i] );
}
static int radeon_emit_packets(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int id = (int)header.packet.packet_id;
int sz = packet[id].len;
static int radeon_emit_scalars(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
static int radeon_emit_scalars2(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n",
start, stride, sz, start + stride * sz);
- if (start + stride * sz > 257) {
+ if (start + stride * sz > 258) {
fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz);
return -1;
}
* Check: table start, end, nr, etc.
*/
static int radeon_emit_vectors(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.vectors.count;
int *data = (int *)cmdbuf->buf;
return 0;
}
+static int radeon_emit_veclinear(
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
+{
+ int sz = header.veclinear.count * 4;
+ int *data = (int *)cmdbuf->buf;
+ float *fdata =(float *)cmdbuf->buf;
+ int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
+ int i;
+
+ if (1||VERBOSE)
+ fprintf(stderr, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n",
+ start, sz >> 2, start + (sz >> 2), header.i);
+
+
+ if (start < 0x60) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start, fdata[i]);
+ fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start, fdata[i+1]);
+ fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start, fdata[i+2]);
+ fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start, fdata[i+3]);
+ }
+ }
+ else if ((start >= 0x100) && (start < 0x160)) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i]);
+ fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+1]);
+ fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+2]);
+ fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+3]);
+ }
+ }
+ else if ((start >= 0x80) && (start < 0xc0)) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x80, data[i]);
+ fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x80, data[i+1]);
+ fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x80, data[i+2]);
+ fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x80, data[i+3]);
+ }
+ }
+ else if ((start >= 0x180) && (start < 0x1c0)) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i]);
+ fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+1]);
+ fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+2]);
+ fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+3]);
+ }
+ }
+ else {
+ fprintf(stderr, "write to unknown vector area\n");
+ }
+
+ cmdbuf->buf += sz * sizeof(int);
+ cmdbuf->bufsz -= sz * sizeof(int);
+ return 0;
+}
+
#if 0
static int print_vertex_format( int vfmt )
{
"TRIANGLE_FAN",
"TRIANGLE_STRIP",
"RECT_LIST",
- 0,
+ NULL,
"3VRT_POINTS",
"3VRT_LINES",
"POINT_SPRITES",
/* build in knowledge about each packet type
*/
-static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
{
int cmdsz;
int *cmd = (int *)cmdbuf->buf;
/* Check cliprects for bounds, then pass on to above:
*/
-static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
{
- XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
+ drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes;
int i = 0;
if (VERBOSE && total_changed) {
int r200SanityCmdBuffer( r200ContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes )
+ drm_clip_rect_t *boxes )
{
int idx;
- drmRadeonCmdBuffer cmdbuf;
- drmRadeonCmdHeader header;
+ drm_radeon_cmd_buffer_t cmdbuf;
+ drm_radeon_cmd_header_t header;
static int inited = 0;
if (!inited) {
cmdbuf.buf = rmesa->store.cmd_buf;
cmdbuf.bufsz = rmesa->store.cmd_used;
- cmdbuf.boxes = (drmClipRect *)boxes;
+ cmdbuf.boxes = (drm_clip_rect_t *)boxes;
cmdbuf.nbox = nbox;
while ( cmdbuf.bufsz >= sizeof(header) ) {
case RADEON_CMD_WAIT:
break;
+ case RADEON_CMD_VECLINEAR:
+ if (radeon_emit_veclinear( header, &cmdbuf )) {
+ fprintf(stderr,"radeon_emit_veclinear failed\n");
+ return -EINVAL;
+ }
+ break;
+
default:
fprintf(stderr,"bad cmd_type %d at %p\n",
header.header.cmd_type,
}
}
- fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__);
+ fprintf(stderr, "leaving %s\n\n\n", __func__);
return 0;
}
projects / mesa.git / blobdiff