-/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_sanity.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
/**************************************************************************
Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
#include <errno.h>
-#include "glheader.h"
-#include "imports.h"
+#include "main/glheader.h"
+#include "main/imports.h"
#include "r200_context.h"
-#include "r200_ioctl.h"
#include "r200_sanity.h"
#include "radeon_reg.h"
#include "r200_reg.h"
#define MORE_VERBOSE 1
#if MORE_VERBOSE
-#define VERBOSE (R200_DEBUG & DEBUG_VERBOSE)
+#define VERBOSE (R200_DEBUG & RADEON_VERBOSE)
#define NORMAL (1)
#else
#define VERBOSE 0
-#define NORMAL (R200_DEBUG & DEBUG_VERBOSE)
+#define NORMAL (R200_DEBUG & RADEON_VERBOSE)
#endif
{ RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+ { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" },
+ { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
+ { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
+ { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
+ { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
+ { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
+ { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
+ { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
+ { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
+ { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
+ { R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
};
struct reg_names {
{ R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
{ R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
{ R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
+ { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" },
{ R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
{ R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
{ R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
{ R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
{ R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
{ R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
+ { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" },
{ R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
{ R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
{ R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
{ R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
{ R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
{ R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
+ { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" },
{ R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
{ R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
{ R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
{ R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
{ R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
{ R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
+ { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" },
{ R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
{ R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
{ R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
{ R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
{ R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
{ R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
+ { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" },
{ R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
{ R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
{ R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
{ R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
{ R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
{ R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
+ { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" },
{ R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
{ R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
{ R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
{ R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
{ R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
{ R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
+ { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" },
+ { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" },
{ R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
{ R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
{ R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
{ R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
{ R200_PP_CNTL_X, "R200_PP_CNTL_X" },
- { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
+ { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
- { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
+ { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
+ { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" },
+ { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" },
+ { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" },
+ { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" },
+ { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" },
+ { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" },
+ { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" },
+ { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" },
+ { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" },
+ { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" },
+ { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" },
+ { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" },
+ { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" },
+ { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" },
+ { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" },
+ { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" },
+ { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" },
+ { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" },
+ { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" },
+ { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" },
+ { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" },
+ { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" },
+ { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" },
+ { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" },
+ { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" },
+ { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" },
+ { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" },
+ { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" },
+ { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" },
+ { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" },
+ { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" },
+ { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" },
+ { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" },
+ { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" },
+ { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" },
+ { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" },
};
static struct reg_names scalar_names[] = {
static int print_reg_assignment( struct reg *reg, int data )
{
+ float_ui32_type datau;
+ datau.ui32 = data;
reg->flags |= TOUCHED;
if (reg->flags & ISFLOAT)
- return print_float_reg_assignment( reg, *(float *)&data );
+ return print_float_reg_assignment( reg, datau.f );
else
return print_int_reg_assignment( reg, data );
}
return 0;
}
+static int radeon_emit_veclinear(
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
+{
+ int sz = header.veclinear.count * 4;
+ int *data = (int *)cmdbuf->buf;
+ float *fdata =(float *)cmdbuf->buf;
+ int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
+ int i;
+
+ if (1||VERBOSE)
+ fprintf(stderr, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n",
+ start, sz >> 2, start + (sz >> 2), header.i);
+
+
+ if (start < 0x60) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start, fdata[i]);
+ fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start, fdata[i+1]);
+ fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start, fdata[i+2]);
+ fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start, fdata[i+3]);
+ }
+ }
+ else if ((start >= 0x100) && (start < 0x160)) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i]);
+ fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+1]);
+ fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+2]);
+ fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+3]);
+ }
+ }
+ else if ((start >= 0x80) && (start < 0xc0)) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x80, data[i]);
+ fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x80, data[i+1]);
+ fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x80, data[i+2]);
+ fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x80, data[i+3]);
+ }
+ }
+ else if ((start >= 0x180) && (start < 0x1c0)) {
+ for (i = 0 ; i < sz ; i += 4) {
+ fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i]);
+ fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+1]);
+ fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+2]);
+ fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+3]);
+ }
+ }
+ else {
+ fprintf(stderr, "write to unknown vector area\n");
+ }
+
+ cmdbuf->buf += sz * sizeof(int);
+ cmdbuf->bufsz -= sz * sizeof(int);
+ return 0;
+}
+
#if 0
static int print_vertex_format( int vfmt )
{
case RADEON_CMD_WAIT:
break;
+ case RADEON_CMD_VECLINEAR:
+ if (radeon_emit_veclinear( header, &cmdbuf )) {
+ fprintf(stderr,"radeon_emit_veclinear failed\n");
+ return -EINVAL;
+ }
+ break;
+
default:
fprintf(stderr,"bad cmd_type %d at %p\n",
header.header.cmd_type,
projects / mesa.git / blobdiff