fix up radeon span functions using latest r200 code from Brian,

[mesa.git] / src / mesa / drivers / dri / r200 / r200_screen.h

diff --git a/src/mesa/drivers/dri/r200/r200_screen.h b/src/mesa/drivers/dri/r200/r200_screen.h
index 845570daf45370848bfc221dd6f36fd3fd8ae27d..c1fa12ed5ef7de3613766e966ded7c0b83958cec 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_screen.h
+++ b/src/mesa/drivers/dri/r200/r200_screen.h
@@ -36,8 +36,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef __R200_SCREEN_H__
 #define __R200_SCREEN_H__
 
-#ifdef GLX_DIRECT_RENDERING
-
 #include "xf86drm.h"
 #include "drm.h"
 #include "radeon_drm.h"
@@ -53,6 +51,8 @@ typedef struct {
 
 /* chipset features */
 #define R200_CHIPSET_TCL       (1 << 0)
+#define R200_CHIPSET_REAL_R200  (1 << 1)
+#define R200_CHIPSET_YCBCR_BROKEN (1 << 2) 
 
 
 #define R200_NR_TEX_HEAPS 2
@@ -86,7 +86,7 @@ typedef struct {
 
    drmBufMapPtr buffers;
 
-   __volatile__ int32_t *scratch;
+   __volatile__ u_int32_t *scratch;       /* is this used for anything? */
 
    __DRIscreenPrivate *driScreen;
    unsigned int sarea_priv_offset;
@@ -94,12 +94,15 @@ typedef struct {
    unsigned int gart_texture_offset;   /* offset in card memory space */
    unsigned int gart_base;
 
-   GLboolean drmSupportsCubeMaps;       /* need radeon kernel module >=1.7 */
+   GLboolean drmSupportsCubeMaps;       /* need radeon kernel module >= 1.7 */
    GLboolean drmSupportsBlendColor;     /* need radeon kernel module >= 1.11 */
+   GLboolean drmSupportsTriPerf;        /* need radeon kernel module >= 1.16 */
+   GLboolean drmSupportsFragShader;     /* need radeon kernel module >= 1.18 */
+   GLboolean drmSupportsPointSprites;   /* need radeon kernel module >= 1.13 */
+   GLboolean depthHasSurface;
 
    /* Configuration cache with default values for all contexts */
    driOptionCache optionCache;
 } r200ScreenRec, *r200ScreenPtr;
 
-#endif
 #endif /* __R200_SCREEN_H__ */